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https://github.com/openhwgroup/cvw
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RAM declaration cleanup:
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@ -38,9 +38,10 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
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input logic [WIDTH-1:0] din,
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input logic [WIDTH-1:0] din,
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input logic we,
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input logic we,
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input logic [(WIDTH-1)/8:0] bwe,
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input logic [(WIDTH-1)/8:0] bwe,
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output logic [WIDTH-1:0] dout);
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:0] RAM[DEPTH-1:0];
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logic [WIDTH-1:0] RAM[DEPTH-1:0];
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// ***************************************************************************
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// ***************************************************************************
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// TRUE SRAM macro
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// TRUE SRAM macro
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@ -64,18 +65,18 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
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integer i;
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integer i;
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// Read
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// Read
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always @(posedge clk)
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always_ff @(posedge clk)
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if(ce) dout <= #1 RAM[addr];
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if(ce) dout <= #1 RAM[addr];
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// Write divided into part for bytes and part for extra msbs
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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if(WIDTH >= 8)
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce & we)
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if (ce & we)
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for(i = 0; i < WIDTH/8; i++)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
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if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce & we & bwe[WIDTH/8])
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if (ce & we & bwe[WIDTH/8])
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RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
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RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
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end
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end
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@ -36,24 +36,20 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module ram2p1r1wb
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module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
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#(parameter int DEPTH = 10,
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input logic clk,
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parameter int WIDTH = 2
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input logic reset,
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)
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(input logic clk,
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// port 1 is read only
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input logic reset,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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// port 1 is read only
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input logic ren1,
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input logic [DEPTH-1:0] ra1,
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output logic [WIDTH-1:0] rd1,
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// port 2 is write only
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input logic ren1,
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input logic [DEPTH-1:0] wa2,
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input logic [WIDTH-1:0] wd2,
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// port 2 is write only
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input logic wen2,
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input logic [DEPTH-1:0] wa2,
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input logic [WIDTH-1:0] bwe2
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input logic [WIDTH-1:0] wd2,
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input logic wen2,
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input logic [WIDTH-1:0] bwe2
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);
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);
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@ -32,16 +32,17 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
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module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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input logic clk,
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input logic ce1, ce2,
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input logic ce1, ce2,
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input logic [$clog2(DEPTH)-1:0] ra1,
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input logic [$clog2(DEPTH)-1:0] ra1,
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input logic [WIDTH-1:0] wd2,
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input logic [WIDTH-1:0] wd2,
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input logic [$clog2(DEPTH)-1:0] wa2,
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input logic [$clog2(DEPTH)-1:0] wa2,
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input logic we2,
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input logic we2,
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input logic [(WIDTH-1)/8:0] bwe2,
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input logic [(WIDTH-1)/8:0] bwe2,
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output logic [WIDTH-1:0] rd1);
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output logic [WIDTH-1:0] rd1
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);
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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// ***************************************************************************
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// ***************************************************************************
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// TRUE Smem macro
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// TRUE Smem macro
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@ -53,18 +54,18 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
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integer i;
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integer i;
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// Read
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// Read
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always @(posedge clk)
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always_ff @(posedge clk)
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if(ce1) rd1 <= #1 mem[ra1];
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if(ce1) rd1 <= #1 mem[ra1];
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// Write divided into part for bytes and part for extra msbs
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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if(WIDTH >= 8)
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce2 & we2)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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always_ff @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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