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Fixed RAM bugs and refactored with read taking place after clock edge rather than before.

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This commit is contained in:
David Harris 2023-02-17 19:14:38 -08:00
parent 9f3c051f8d
commit a194740562
2 changed files with 22 additions and 11 deletions
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12
src/generic/mem/ram1p1rwbe.sv
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@ -34,7 +34,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) ( module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
input logic clk, input logic clk,
input logic ce, input logic ce,
input logic [$clog2(DEPTH)-1:0] addr, input logic [$clog2(DEPTH)-1:0] addr,
@ -69,7 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) (
.A(addr), .D(din), .A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout)); .BWEB(~BitWriteMask), .Q(dout));
end else if (`USE_SRAM == 1 & WIDTH == 22 & DEPTH == 32) begin // RV32 cache tag end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag
genvar index; genvar index;
// 64 x 22-bit SRAM // 64 x 22-bit SRAM
logic [WIDTH-1:0] BitWriteMask; logic [WIDTH-1:0] BitWriteMask;
@ -86,8 +86,14 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) (
integer i; integer i;
// Read // Read
logic [$clog2(DEPTH)-1:0] addrd;
flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
assign dout = RAM[addrd];
/* // Read
always_ff @(posedge clk) always_ff @(posedge clk)
if(ce) dout <= #1 RAM[addr]; if(ce) dout <= #1 mem[addr]; */
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.

15
src/generic/mem/ram2p1r1wbe.sv
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@ -33,7 +33,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
input logic clk, input logic clk,
input logic ce1, ce2, input logic ce1, ce2,
input logic [$clog2(DEPTH)-1:0] ra1, input logic [$clog2(DEPTH)-1:0] ra1,
@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
// TRUE Smem macro // TRUE Smem macro
// *************************************************************************** // ***************************************************************************
if (`USE_SRAM == 1 & WIDTH == 68 & DEPTH == 1024) begin if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
.CEBA(~ce1), .CEBB(~ce2), .CEBA(~ce1), .CEBB(~ce2),
@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
.QA(rd1), .QA(rd1),
.QB()); .QB());
end else if (`USE_SRAM == 1 & WIDTH == 36 & DEPTH == 1024) begin end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk),
.CEBA(~ce1), .CEBB(~ce2), .CEBA(~ce1), .CEBB(~ce2),
@ -76,7 +76,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
.QA(rd1), .QA(rd1),
.QB()); .QB());
end else if (`USE_SRAM == 1 & WIDTH == 2 & DEPTH == 1024) begin end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMReadData;
logic [SRAMWIDTH-1:0] SRAMWriteData; logic [SRAMWIDTH-1:0] SRAMWriteData;
@ -114,8 +114,13 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
integer i; integer i;
// Read // Read
logic [$clog2(DEPTH)-1:0] ra1d;
flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
assign rd1 = mem[ra1d];
/* // Read
always_ff @(posedge clk) always_ff @(posedge clk)
if(ce1) rd1 <= #1 mem[ra1]; if(ce1) rd1 <= #1 mem[ra1]; */
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
if(WIDTH >= 8) if(WIDTH >= 8)