diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index ede8f258e..14bbc15b6 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -425,5 +425,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // the synchronous DTIM cannot read immediately after write
   // a cache cannot read or write immediately after a write
   // atomic operations are also detected as MemRWD[1]
-  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
+  //assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
+  // *** RT: Modify for ZICBOZ
+  assign StoreStallD = (MemRWE[0] | (|CMOpE & P.ZICBOM_SUPPORTED)) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | (|CMOpD & P.ZICBOM_SUPPORTED)));
 endmodule