From a130a96b45b73b25ef480d2142a29fb825f59bd5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 4 Dec 2022 01:20:51 -0600 Subject: [PATCH] Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. --- pipelined/src/cache/cacheway.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 38913bc44..6865bf110 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -85,7 +85,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, mux2 #(1) selectedwaymux(HitWay, SelTag, SelFlush | SetValid, SelectedWay); - // RT: Can we merge these two muxes? + // RT: Can we merge these two muxes? This is also shared in cacheLRU. // mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelectedWay); //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);