From 56cc04316c01d7f1e2a8a41c6ec7e401fa870626 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 2 Oct 2022 16:21:21 -0500 Subject: [PATCH 01/32] Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered. --- pipelined/src/privileged/trap.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 2c3c0f21e..039944919 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -50,6 +50,8 @@ module trap ( logic MIntGlobalEnM, SIntGlobalEnM; logic ExceptionM; + logic Committed; + (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; /////////////////////////////////////////// @@ -62,8 +64,9 @@ module trap ( assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; - assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW; - assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM | CommittedF); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide. + assign Committed = CommittedM | CommittedF; + assign ValidIntsM = {12{~Committed}} & ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); + assign InterruptM = (|ValidIntsM) && InstrValidM && ~Committed; // suppress interrupt if the memory system has partially processed a request. assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); From 175e824a618206ee348df407ea84c97712613ba9 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 4 Oct 2022 17:33:49 +0000 Subject: [PATCH 02/32] Renamed endianswap to match module name --- pipelined/regression/sim-wally-batch | 2 +- pipelined/src/lsu/bigendianswap.sv | 79 ---------------------------- 2 files changed, 1 insertion(+), 80 deletions(-) delete mode 100644 pipelined/src/lsu/bigendianswap.sv diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch index afaf935c6..e9a387d0a 100755 --- a/pipelined/regression/sim-wally-batch +++ b/pipelined/regression/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-pipelined-batch.do rv32ic arch32i" +vsim -c -do "do wally-pipelined-batch.do rv32gc wally32priv" diff --git a/pipelined/src/lsu/bigendianswap.sv b/pipelined/src/lsu/bigendianswap.sv deleted file mode 100644 index e621afcfc..000000000 --- a/pipelined/src/lsu/bigendianswap.sv +++ /dev/null @@ -1,79 +0,0 @@ -/////////////////////////////////////////// -// endianswap.sv -// -// Written: David_Harris@hmc.edu 7 May 2022 -// Modified: -// -// Purpose: Swap byte order for Big-Endian accesses -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module endianswap #(parameter LEN=`XLEN) ( - input logic BigEndianM, - input logic [LEN-1:0] a, - output logic [LEN-1:0] y); - - if(LEN == 128) begin - always_comb - if (BigEndianM) begin // swap endianness - y[127:120] = a[7:0]; - y[119:112] = a[15:8]; - y[111:104] = a[23:16]; - y[103:96] = a[31:24]; - y[95:88] = a[39:32]; - y[87:80] = a[47:40]; - y[79:72] = a[55:48]; - y[71:64] = a[63:56]; - y[63:56] = a[71:64]; - y[55:48] = a[79:72]; - y[47:40] = a[87:80]; - y[39:32] = a[95:88]; - y[31:24] = a[103:96]; - y[23:16] = a[111:104]; - y[15:8] = a[119:112]; - y[7:0] = a[127:120]; - end else y = a; - end else if(LEN == 64) begin - always_comb - if (BigEndianM) begin // swap endianness - y[63:56] = a[7:0]; - y[55:48] = a[15:8]; - y[47:40] = a[23:16]; - y[39:32] = a[31:24]; - y[31:24] = a[39:32]; - y[23:16] = a[47:40]; - y[15:8] = a[55:48]; - y[7:0] = a[63:56]; - end else y = a; - end else begin - always_comb - if (BigEndianM) begin - y[31:24] = a[7:0]; - y[23:16] = a[15:8]; - y[15:8] = a[23:16]; - y[7:0] = a[31:24]; - end else y = a; - end -endmodule From 2bbcec680fb7862722c2204b944f589a080daef6 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 4 Oct 2022 17:37:05 +0000 Subject: [PATCH 03/32] addded renamed file --- pipelined/src/lsu/endianswap.sv | 79 +++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 pipelined/src/lsu/endianswap.sv diff --git a/pipelined/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv new file mode 100644 index 000000000..e621afcfc --- /dev/null +++ b/pipelined/src/lsu/endianswap.sv @@ -0,0 +1,79 @@ +/////////////////////////////////////////// +// endianswap.sv +// +// Written: David_Harris@hmc.edu 7 May 2022 +// Modified: +// +// Purpose: Swap byte order for Big-Endian accesses +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module endianswap #(parameter LEN=`XLEN) ( + input logic BigEndianM, + input logic [LEN-1:0] a, + output logic [LEN-1:0] y); + + if(LEN == 128) begin + always_comb + if (BigEndianM) begin // swap endianness + y[127:120] = a[7:0]; + y[119:112] = a[15:8]; + y[111:104] = a[23:16]; + y[103:96] = a[31:24]; + y[95:88] = a[39:32]; + y[87:80] = a[47:40]; + y[79:72] = a[55:48]; + y[71:64] = a[63:56]; + y[63:56] = a[71:64]; + y[55:48] = a[79:72]; + y[47:40] = a[87:80]; + y[39:32] = a[95:88]; + y[31:24] = a[103:96]; + y[23:16] = a[111:104]; + y[15:8] = a[119:112]; + y[7:0] = a[127:120]; + end else y = a; + end else if(LEN == 64) begin + always_comb + if (BigEndianM) begin // swap endianness + y[63:56] = a[7:0]; + y[55:48] = a[15:8]; + y[47:40] = a[23:16]; + y[39:32] = a[31:24]; + y[31:24] = a[39:32]; + y[23:16] = a[47:40]; + y[15:8] = a[55:48]; + y[7:0] = a[63:56]; + end else y = a; + end else begin + always_comb + if (BigEndianM) begin + y[31:24] = a[7:0]; + y[23:16] = a[15:8]; + y[15:8] = a[23:16]; + y[7:0] = a[31:24]; + end else y = a; + end +endmodule From d5cd67cf09c5d0f877796222a21e40188195e517 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 4 Oct 2022 17:37:39 +0000 Subject: [PATCH 04/32] fixed endianness mstatush problem, passes make, not regression --- pipelined/testbench/tests.vh | 6 ++++-- .../rv32i_m/privilege/src/WALLY-endianness-01.S | 17 ++++++++++------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 61e76ff15..b6c7c790f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1818,7 +1818,8 @@ string imperas32f[] = '{ "rv64i_m/privilege/src/WALLY-trap-sret-01.S", "rv64i_m/privilege/src/WALLY-trap-u-01.S", "rv64i_m/privilege/src/WALLY-wfi-01.S", - "rv64i_m/privilege/src/WALLY-endianness-01.S" + "rv64i_m/privilege/src/WALLY-endianness-01.S", + "rv64i_m/privilege/src/WALLY-status-xlen-01.S" }; string wally64periph[] = '{ @@ -1896,7 +1897,8 @@ string imperas32f[] = '{ "rv32i_m/privilege/src/WALLY-trap-s-01.S", "rv32i_m/privilege/src/WALLY-trap-sret-01.S", "rv32i_m/privilege/src/WALLY-trap-u-01.S", - "rv32i_m/privilege/src/WALLY-wfi-01.S" + "rv32i_m/privilege/src/WALLY-wfi-01.S", + "rv32i_m/privilege/src/WALLY-endianness-01.S" }; string wally32periph[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S index e51a6b65b..c13dde253 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S @@ -58,7 +58,7 @@ addi t1, t1, 4 addi a6, a6, 4 li x28, 0x20 -csrs mstatush, x28 // turn on big endianness for M mode +csrs 0x310, x28 // turn on big endianness for M mode // using '0x310' instead of mstatush because GCC doesn't recognize just mstatush // M mode Big endianness tests // In big endian modes, all values are sign extended to the right, rather than left @@ -83,7 +83,7 @@ addi t1, t1, 4 addi a6, a6, 4 li x28, 0x20 -csrc mstatush, x28 // Turn off big endianness for M mode before going into the trap handler +csrc 0x310, x28 // Turn off big endianness for M mode before going into the trap handler // using '0x310' instead of mstatush because GCC doesn't recognize just mstatush GOTO_S_MODE @@ -91,7 +91,7 @@ GOTO_S_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xAABBCCDD +sw x28, 0(x29) // value stored in memory as 0xAABBCCDD lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xAABBCCDD @@ -111,7 +111,7 @@ addi a6, a6, 4 GOTO_M_MODE // Go back to M mode to be able to toggle SBE bit of mstatus li x28, 0x10 -csrs mstatush, x28 // turn on big endianness for S mode +csrs 0x310, x28 // turn on big endianness for S mode // using '0x310' instead of mstatush because GCC doesn't recognize just mstatush GOTO_S_MODE @@ -119,7 +119,7 @@ GOTO_S_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA +sw x28, 0(x29) // value stored in memory as 0xDDCCBBAA lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xDDCCBBAA @@ -142,7 +142,7 @@ GOTO_U_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xAABBCCDD +sw x28, 0(x29) // value stored in memory as 0xAABBCCDD lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xAABBCCDD @@ -170,7 +170,7 @@ GOTO_U_MODE li x28, 0xAABBCCDD li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA +sw x28, 0(x29) // value stored in memory as 0xDDCCBBAA lw x30, 0(x29) // test load word, should read out 0xAABBCCDD sw x30, 0(t1) // test store word, should save 0xDDCCBBAA @@ -187,6 +187,9 @@ sb x30, 0(t1) // test store byte, should save 0xAA addi t1, t1, 4 addi a6, a6, 4 +//store_location: +//.fill + END_TESTS TEST_STACK_AND_DATA \ No newline at end of file From 52e8e0f5efbc55db5c3abf5a9d147cf7740ad671 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 4 Oct 2022 15:14:58 -0500 Subject: [PATCH 05/32] Modified cache lru to not have the delayed write. --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cachereplacementpolicy.sv | 16 +++++++--------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index ae52a1088..b72a61360 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -133,7 +133,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE .Invalidate(InvalidateCache)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .HitWay, .VictimWay, .RAdr, .LRUWriteEn); + .clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index d407bc284..decef7b76 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -31,7 +31,7 @@ module cachereplacementpolicy #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( - input logic clk, reset, + input logic clk, reset, ce, input logic [NUMWAYS-1:0] HitWay, output logic [NUMWAYS-1:0] VictimWay, input logic [SETLEN-1:0] RAdr, @@ -51,17 +51,15 @@ module cachereplacementpolicy assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported"); end - // Pipeline Delay Registers - flopr #(SETLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD); - flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD); - flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD); - // Replacement Bits: Register file // Needs to be resettable for simulation, but could omit reset for synthesis *** - always_ff @(posedge clk) + always_ff @(posedge clk) begin if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0; - else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD; - assign LineReplacementBits = ReplacementBits[RAdrD]; + if(ce) begin + LineReplacementBits <= #1 ReplacementBits[RAdr]; + if (LRUWriteEn) ReplacementBits[RAdr] <= NewReplacement; + end + end genvar index; if(NUMWAYS == 2) begin : PseudoLRU From 8f18bb9243599b683820909742d677cef9b3ae40 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 4 Oct 2022 17:35:44 -0500 Subject: [PATCH 06/32] Updated constraints file to work with alternate uart. --- fpga/constraints/constraints.xdc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc index 6b0a0363c..b21b1cc51 100644 --- a/fpga/constraints/constraints.xdc +++ b/fpga/constraints/constraints.xdc @@ -35,12 +35,14 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por ##### UART ##### -set_property PACKAGE_PIN AW25 [get_ports UARTSin] -set_property PACKAGE_PIN BB21 [get_ports UARTSout] +#set_property PACKAGE_PIN AW25 [get_ports UARTSin] +set_property PACKAGE_PIN R29 [get_ports UARTSin] +#set_property PACKAGE_PIN BB21 [get_ports UARTSout] +set_property PACKAGE_PIN M31 [get_ports UARTSout] set_max_delay -from [get_ports UARTSin] 10.000 set_max_delay -to [get_ports UARTSout] 10.000 -set_property IOSTANDARD LVCMOS18 [get_ports UARTSin] -set_property IOSTANDARD LVCMOS18 [get_ports UARTSout] +set_property IOSTANDARD LVCMOS12 [get_ports UARTSin] +set_property IOSTANDARD LVCMOS12 [get_ports UARTSout] set_property DRIVE 6 [get_ports UARTSout] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin] From 92d7be645b6a463400a3661fc4471f4bd069dc00 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 4 Oct 2022 15:29:32 -0500 Subject: [PATCH 07/32] Reordered the eviction and fetch in cache so it follows a more logical order. --- pipelined/src/cache/cachefsm.sv | 22 ++++++++++--------- pipelined/src/cache/cachereplacementpolicy.sv | 8 +++++-- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 58ae7afba..94bf36a6a 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -133,17 +133,17 @@ module cachefsm else if(DoFlush) NextState = STATE_FLUSH; // Delayed LRU update. Cannot check if victim line is dirty on this cycle. // To optimize do the fetch first, then eviction if necessary. - else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; + else if(DoAnyMiss & ~VictimDirty) NextState = STATE_MISS_FETCH_WDV; + else if(DoAnyMiss & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_READY; - STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE; - else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; else NextState = STATE_MISS_FETCH_WDV; //STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; - STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY; + STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY; //else NextState = STATE_READY; STATE_MISS_READ_DELAY: if(CPUBusy) NextState = STATE_MISS_READ_DELAY; else NextState = STATE_READY; - STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; + STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV; else NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. STATE_FLUSH: NextState = STATE_FLUSH_CHECK; @@ -174,15 +174,15 @@ module cachefsm // write enables internal to cache assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0])); + (CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0])); assign ClearValid = '0; assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | (CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck); assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | (CurrState == STATE_MISS_WRITE_CACHE_LINE); // Flush and eviction controls - assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty); + assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | + (CurrState == STATE_READY & DoAnyMiss & VictimDirty); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK); assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; @@ -193,9 +193,11 @@ module cachefsm assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls - assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck); + assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss & ~VictimDirty) | + (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck) | + (CurrState == STATE_MISS_EVICT_DIRTY & CacheBusAck); // assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss; - assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | + assign CacheBusRW[0] = (CurrState == STATE_READY & DoAnyMiss & VictimDirty) | (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index decef7b76..a791e9fcc 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -56,8 +56,12 @@ module cachereplacementpolicy always_ff @(posedge clk) begin if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0; if(ce) begin - LineReplacementBits <= #1 ReplacementBits[RAdr]; - if (LRUWriteEn) ReplacementBits[RAdr] <= NewReplacement; + if (LRUWriteEn) begin + ReplacementBits[RAdr] <= NewReplacement; + LineReplacementBits <= #1 NewReplacement; + end else begin + LineReplacementBits <= #1 ReplacementBits[RAdr]; + end end end From e6b36d0c022607e9f3f327ddc6d7d1d312f28fbf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 10:58:23 -0500 Subject: [PATCH 08/32] Optimized the ebu's beat counting. --- pipelined/src/ebu/ebu.sv | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index c4cb882d6..5276c9e8b 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -94,7 +94,7 @@ module ebu logic BeatCntEn; logic [4-1:0] NextBeatCount, BeatCount, BeatCountDelayed; - logic FinalBeat; + logic FinalBeat, FinalBeatD; logic [2:0] LocalBurstType; logic CntReset; logic [3:0] Threshold; @@ -145,7 +145,7 @@ module ebu case (CurrState) IDLE: if (both) NextState = ARBITRATE; else NextState = IDLE; - ARBITRATE: if (HREADY & FinalBeat & ~(LSUReq & IFUReq)) NextState = IDLE; + ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE; else NextState = ARBITRATE; default: NextState = IDLE; endcase @@ -154,31 +154,29 @@ module ebu // Controller needs to count beats. flopenr #(4) BeatCountReg(.clk(HCLK), - .reset(~HRESETn | CntReset | FinalBeat), + .reset(~HRESETn | CntReset | FinalBeatD), .en(BeatCntEn), .d(NextBeatCount), .q(BeatCount)); - - // Used to store data from data phase of AHB. - flopenr #(4) - BeatCountDelayedReg(.clk(HCLK), - .reset(~HRESETn | CntReset), - .en(BeatCntEn), - .d(BeatCount), - .q(BeatCountDelayed)); assign NextBeatCount = BeatCount + 1'b1; assign CntReset = NextState == IDLE; - assign FinalBeat = (BeatCountDelayed == Threshold); // Detect when we are waiting on the final access. + assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. assign BeatCntEn = (NextState == ARBITRATE & HREADY); logic [2:0] HBURSTD; - flopenr #(3) HBURSTReg(.clk(HCLK), .reset(~HRESETn), .en(HTRANS == 2'b10), .d(HBURST), .q(HBURSTD)); + // Used to store data from data phase of AHB. + flopenr #(1) + FinalBeatReg(.clk(HCLK), + .reset(~HRESETn | CntReset), + .en(BeatCntEn), + .d(FinalBeat), + .q(FinalBeatD)); // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. always_comb begin - case(HBURSTD) + case(HBURST) 0: Threshold = 4'b0000; 3: Threshold = 4'b0011; // INCR4 5: Threshold = 4'b0111; // INCR8 @@ -196,7 +194,7 @@ module ebu assign IFUDisable = CurrState == ARBITRATE; assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq; // Controller 1 (LSU) - assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeat)); + assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD)); assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq; flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD); From f318daa6051c957da59b0e04d8cfc9296f062394 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 5 Oct 2022 11:45:31 -0700 Subject: [PATCH 09/32] Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests. --- pipelined/config/rv32i/wally-config.vh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index a0ea4607e..09c14606a 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -51,9 +51,9 @@ `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features `define BUS 1 -`define DCACHE 1 -`define ICACHE 1 -`define VIRTMEM_SUPPORTED 1 +`define DCACHE 0 +`define ICACHE 0 +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 @@ -86,16 +86,16 @@ // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b0 +`define DTIM_SUPPORTED 1'b1 `define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF -`define IROM_SUPPORTED 1'b0 +`define DTIM_RANGE 34'h07FFFFFF +`define IROM_SUPPORTED 1'b1 `define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define IROM_RANGE 34'h07FFFFFF `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_SUPPORTED 1'b0 `define UNCORE_RAM_BASE 34'h80000000 `define UNCORE_RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 From 68aa1434b4dfb5131bb260733dbc5c2b0cea2161 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 14:51:02 -0500 Subject: [PATCH 10/32] Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. Don't use this commit as the rv32i tests are not passing. --- pipelined/src/ifu/ifu.sv | 25 ++++++++++++++-------- pipelined/src/lsu/lsu.sv | 37 ++++++++++++++++++++------------- pipelined/src/mmu/mmu.sv | 4 ++-- pipelined/src/mmu/pmachecker.sv | 3 ++- 4 files changed, 42 insertions(+), 27 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 8bda30b0d..35bd22ff2 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -91,7 +91,7 @@ module ifu ( logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; - logic [31:0] InstrRawD, InstrRawF; + logic [31:0] InstrRawD, InstrRawF, InstrRaw2F, IROMInstrRawF, ICacheInstrRawF; logic [31:0] FinalInstrRawF; logic [1:0] IFURWF; @@ -118,6 +118,8 @@ module ifu ( // branch predictor signal logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F; logic BusCommittedF, CacheCommittedF; + logic SelIROM; + assign PCFExt = {2'b00, PCFSpill}; @@ -128,7 +130,7 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport - spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, + spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRaw2F), .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport @@ -166,7 +168,7 @@ module ifu ( .TLBFlush, .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), - .Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(), + .Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(), .SelTIM(SelIROM), .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(), .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(), .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(), @@ -196,7 +198,7 @@ module ifu ( // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (`IROM_SUPPORTED) begin : irom assign IFURWF = 2'b10; - irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(FinalInstrRawF)); + irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrRawF)); end else begin assign IFURWF = 2'b10; @@ -222,7 +224,7 @@ module ifu ( .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, - .ReadDataWord(FinalInstrRawF), + .ReadDataWord(ICacheInstrRawF), .Cacheable(CacheableF), .SelReplay('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), @@ -244,11 +246,14 @@ module ifu ( .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedF)); - mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), - .s(SelUncachedAdr), .y(InstrRawF[31:0])); + mux2 #(32) UnCachedDataMux(.d0(ICacheInstrRawF), .d1(FetchBuffer[32-1:0]), + .s(SelUncachedAdr), .y(InstrRawF)); + mux2 #(32) UnCachedDataMux2(.d0(InstrRawF), .d1(IROMInstrRawF), + .s(SelIROM), .y(InstrRaw2F[31:0])); end else begin : passthrough assign IFUHADDR = PCPF; logic CaptureEn; + logic [31:0] FetchBuffer; logic [1:0] BusRW; assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{TrapM, TrapM}; assign IFUHSIZE = 3'b010; @@ -256,8 +261,10 @@ module ifu ( ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), - .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(InstrRawF[31:0])); + .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); + if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrRawF, SelIROM, InstrRaw2F); + else assign InstrRaw2F = FetchBuffer; assign IFUHBURST = 3'b0; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; assign {ICacheMiss, ICacheAccess} = '0; @@ -265,7 +272,7 @@ module ifu ( end else begin : nobus // block: bus assign BusStall = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; - assign InstrRawF = FinalInstrRawF; + assign InstrRaw2F = IROMInstrRawF; end assign IFUCacheBusStallF = ICacheStallF | BusStall; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 0d08e3fae..4c775107e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -117,6 +117,7 @@ module lsu ( logic [`LLEN-1:0] ReadDataM; logic [(`LLEN-1)/8:0] ByteMaskM; logic SelReplay; + logic SelDTIM; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); assign IEUAdrExtM = {2'b00, IEUAdrM}; @@ -168,7 +169,7 @@ module lsu ( .TLBFlush(sfencevmaM), .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), - .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), + .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), .SelTIM(SelDTIM), .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM, .InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw. @@ -200,19 +201,21 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// logic [`LLEN-1:0] LSUWriteDataM, LittleEndianWriteDataM; logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; - logic [`LLEN-1:0] ReadDataWordMuxM; + logic [`LLEN-1:0] ReadDataWordMuxM, DTIMReadDataWordM, ReadDataWordMux2M, DCacheReadDataWordM; logic IgnoreRequest; assign IgnoreRequest = IgnoreRequestTLB | TrapM; if (`DTIM_SUPPORTED) begin : dtim logic [`PA_BITS-1:0] DTIMAdr; - + logic [1:0] DTIMMemRWM; + // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. assign DTIMAdr = MemRWM[0] ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS - dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM, + assign DTIMMemRWM = LSURWM & ~{IgnoreRequest, IgnoreRequest} & {SelDTIM, SelDTIM}; + dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), .Adr(DTIMAdr), .TrapM, .WriteDataM(LSUWriteDataM), - .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); + .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); end else begin end if (`BUS) begin : bus @@ -231,7 +234,7 @@ module lsu ( logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; - assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}; + assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM} & ~{SelDTIM, SelDTIM}; cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( @@ -241,7 +244,7 @@ module lsu ( .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM), .SelReplay, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), - .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), + .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) ahbcacheinterface( @@ -254,9 +257,11 @@ module lsu ( .SelUncachedAdr, .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); - mux2 #(`LLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), + mux2 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), + mux2 #(`LLEN) ReadDataMux2(.d0(ReadDataWordMuxM), .d1({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), + .s(SelUncachedAdr), .y(ReadDataWordMux2M)); + mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(PreHWDATA)); flopen #(`XLEN) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN @@ -271,6 +276,7 @@ module lsu ( end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn; logic [1:0] BusRW; + logic [`XLEN-1:0] FetchBuffer; assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest}; assign LSUHADDR = PAdrM; @@ -279,15 +285,16 @@ module lsu ( ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), - .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(ReadDataWordM)); - - assign ReadDataWordMuxM = ReadDataWordM; // from byte swapping + .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + + if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMux2M); + else assign ReadDataWordMux2M = FetchBuffer[`XLEN-1:0]; assign LSUHBURST = 3'b0; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; end end else begin: nobus // block: bus assign LSUHWDATA = '0; - assign ReadDataWordMuxM = ReadDataWordM; + assign ReadDataWordMux2M = DTIMReadDataWordM; assign {BusStall, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM} = '0; @@ -334,10 +341,10 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// if (`BIGENDIAN_SUPPORTED) begin:endian endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); - endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); + endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMux2M), .y(LittleEndianReadDataWordM)); end else begin assign LSUWriteDataM = LittleEndianWriteDataM; - assign LittleEndianReadDataWordM = ReadDataWordMuxM; + assign LittleEndianReadDataWordM = ReadDataWordMux2M; end endmodule diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index dbf23e98e..da90ee2ca 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -66,7 +66,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries // Physical address outputs output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, - output logic Cacheable, Idempotent, AtomicAllowed, + output logic Cacheable, Idempotent, AtomicAllowed, SelTIM, // Faults output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, @@ -126,7 +126,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries pmachecker pmachecker(.PhysicalAddress, .Size, .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, - .Cacheable, .Idempotent, .AtomicAllowed, + .Cacheable, .Idempotent, .AtomicAllowed, .SelTIM, .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW, diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index 455f510dc..df6eb271c 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -38,7 +38,7 @@ module pmachecker ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic [1:0] Size, input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use. - output logic Cacheable, Idempotent, AtomicAllowed, + output logic Cacheable, Idempotent, AtomicAllowed, SelTIM, output logic PMAInstrAccessFaultF, output logic PMALoadAccessFaultM, output logic PMAStoreAmoAccessFaultM @@ -60,6 +60,7 @@ module pmachecker ( assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6]; assign AtomicAllowed = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6]; + assign SelTIM = SelRegions[10] | SelRegions[9]; // Detect access faults assign PMAAccessFault = (SelRegions[0]) & AccessRWX; From a0c5833d6dfa476adaa9383b6548f66c46b49228 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 14:51:12 -0500 Subject: [PATCH 11/32] Fixed bug in EBU. --- pipelined/src/ebu/ebu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index 5276c9e8b..d4c992426 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -154,7 +154,7 @@ module ebu // Controller needs to count beats. flopenr #(4) BeatCountReg(.clk(HCLK), - .reset(~HRESETn | CntReset | FinalBeatD), + .reset(~HRESETn | CntReset | FinalBeat), .en(BeatCntEn), .d(NextBeatCount), .q(BeatCount)); From 8d01cf32fc81c072360f446b3685eeecf93675ad Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 14:55:40 -0500 Subject: [PATCH 12/32] Updated wavefile. --- pipelined/regression/wave.do | 203 ++++++++++++++++++----------------- 1 file changed, 103 insertions(+), 100 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 6b5e51306..93db10362 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -5,56 +5,56 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ifu/InstrD -add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D -add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD +add wave -noupdate -group {Decode Stage} /testbench/InstrDName +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName @@ -125,12 +125,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/if add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/core/PCF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/core/PCE -add wave -noupdate -expand -group PCS /testbench/dut/core/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/core/PCF +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/core/PCE +add wave -noupdate -group PCS /testbench/dut/core/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F @@ -169,47 +169,49 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCountDelayed -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURSTD -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA -add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -expand -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount +add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURSTD +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY +add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/HRDATA +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/HRDATA +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB +add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA +add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall @@ -581,9 +583,10 @@ add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[ add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/Valid} +add wave -noupdate /testbench/dut/core/priv/priv/InterruptM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {364546 ns} 1} {{Cursor 3} {678624 ns} 0} {{Cursor 4} {378225 ns} 1} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 2} {200566 ns} 0} {{Cursor 3} {190821 ns} 1} {{Cursor 4} {378225 ns} 1} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -598,4 +601,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {678593 ns} {678769 ns} +WaveRestoreZoom {200403 ns} {200739 ns} From b52ab91028b1bbbc10411f4ec0f2adc1494e7ee0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 15:08:20 -0500 Subject: [PATCH 13/32] Possibly have working dtim + bus config. --- pipelined/src/ifu/ifu.sv | 8 ++++---- pipelined/src/lsu/lsu.sv | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 35bd22ff2..af43f21ce 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -136,7 +136,7 @@ module ifu ( end else begin : NoSpillSupport assign PCNextFSpill = PCNextF; assign PCFSpill = PCF; - assign PostSpillInstrRawF = InstrRawF; + assign PostSpillInstrRawF = InstrRaw2F; assign {SelNextSpillF, CompressedF} = 0; end @@ -198,7 +198,7 @@ module ifu ( // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (`IROM_SUPPORTED) begin : irom assign IFURWF = 2'b10; - irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrRawF)); + irom irom(.clk, .reset, .ce(~CPUBusy | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrRawF)); end else begin assign IFURWF = 2'b10; @@ -216,7 +216,7 @@ module ifu ( logic IgnoreRequest; assign IgnoreRequest = ITLBMissF | TrapM; - assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF}; + assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) @@ -255,7 +255,7 @@ module ifu ( logic CaptureEn; logic [31:0] FetchBuffer; logic [1:0] BusRW; - assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{TrapM, TrapM}; + assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{TrapM, TrapM} & ~{SelIROM, SelIROM}; assign IFUHSIZE = 3'b010; ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 4c775107e..a5f9c73ef 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -277,7 +277,7 @@ module lsu ( logic CaptureEn; logic [1:0] BusRW; logic [`XLEN-1:0] FetchBuffer; - assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest}; + assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{SelDTIM, SelDTIM}; assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; From 2e578eb8d86a024ca9838126ef04b173fd1eb1e8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 15:16:01 -0500 Subject: [PATCH 14/32] Fixed bug with combined dtim+bus. --- pipelined/src/lsu/lsu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index a5f9c73ef..77f807ff2 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -260,7 +260,7 @@ module lsu ( mux2 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`LLEN) ReadDataMux2(.d0(ReadDataWordMuxM), .d1({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), - .s(SelUncachedAdr), .y(ReadDataWordMux2M)); + .s(SelDTIM), .y(ReadDataWordMux2M)); mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(PreHWDATA)); From 2144343c4a73f4a92e4db0d0b86124788e0874b8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 15:36:56 -0500 Subject: [PATCH 15/32] Name clarifications. --- pipelined/src/ifu/ifu.sv | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index af43f21ce..2f9c6f0a1 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -91,7 +91,7 @@ module ifu ( logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; - logic [31:0] InstrRawD, InstrRawF, InstrRaw2F, IROMInstrRawF, ICacheInstrRawF; + logic [31:0] InstrRawD, InstrRawF, IROMInstrF, ICacheInstrF; logic [31:0] FinalInstrRawF; logic [1:0] IFURWF; @@ -130,13 +130,13 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport - spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRaw2F), + spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF), .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport assign PCNextFSpill = PCNextF; assign PCFSpill = PCF; - assign PostSpillInstrRawF = InstrRaw2F; + assign PostSpillInstrRawF = InstrRawF; assign {SelNextSpillF, CompressedF} = 0; end @@ -180,6 +180,7 @@ module ifu ( assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0; assign PCPF = PCFExt[`PA_BITS-1:0]; assign CacheableF = '1; + assign SelIROM = '0; end //////////////////////////////////////////////////////////////////////////////////////////////// @@ -192,13 +193,13 @@ module ifu ( // delay the interrupt until the LSU is in a clean state. assign CommittedF = CacheCommittedF | BusCommittedF; -// logic [`XLEN-1:0] InstrRawF; -// assign InstrRawF = InstrRawF[31:0]; + logic IgnoreRequest; + assign IgnoreRequest = ITLBMissF | TrapM; // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (`IROM_SUPPORTED) begin : irom assign IFURWF = 2'b10; - irom irom(.clk, .reset, .ce(~CPUBusy | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrRawF)); + irom irom(.clk, .reset, .ce(~CPUBusy | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF)); end else begin assign IFURWF = 2'b10; @@ -213,9 +214,8 @@ module ifu ( logic ICacheBusAck; logic SelUncachedAdr; logic [1:0] CacheBusRW, BusRW; - logic IgnoreRequest; + - assign IgnoreRequest = ITLBMissF | TrapM; assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), @@ -224,7 +224,7 @@ module ifu ( .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, - .ReadDataWord(ICacheInstrRawF), + .ReadDataWord(ICacheInstrF), .Cacheable(CacheableF), .SelReplay('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), @@ -246,16 +246,14 @@ module ifu ( .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedF)); - mux2 #(32) UnCachedDataMux(.d0(ICacheInstrRawF), .d1(FetchBuffer[32-1:0]), - .s(SelUncachedAdr), .y(InstrRawF)); - mux2 #(32) UnCachedDataMux2(.d0(InstrRawF), .d1(IROMInstrRawF), - .s(SelIROM), .y(InstrRaw2F[31:0])); + mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF), + .s({SelIROM, SelUncachedAdr}), .y(InstrRawF[31:0])); end else begin : passthrough assign IFUHADDR = PCPF; logic CaptureEn; logic [31:0] FetchBuffer; logic [1:0] BusRW; - assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{TrapM, TrapM} & ~{SelIROM, SelIROM}; + assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM}; assign IFUHSIZE = 3'b010; ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), @@ -263,8 +261,8 @@ module ifu ( .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); - if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrRawF, SelIROM, InstrRaw2F); - else assign InstrRaw2F = FetchBuffer; + if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); + else assign InstrRawF = FetchBuffer; assign IFUHBURST = 3'b0; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; assign {ICacheMiss, ICacheAccess} = '0; @@ -272,7 +270,7 @@ module ifu ( end else begin : nobus // block: bus assign BusStall = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; - assign InstrRaw2F = IROMInstrRawF; + assign InstrRawF = IROMInstrF; end assign IFUCacheBusStallF = ICacheStallF | BusStall; From 62951ec653303d36686c9febf65452000ca64ebb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 15:37:01 -0500 Subject: [PATCH 16/32] Fixed wally32e. --- pipelined/src/lsu/lsu.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 77f807ff2..8e7059742 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -193,6 +193,7 @@ module lsu ( assign {LoadPageFaultM, StoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM; assign CacheableM = '1; + assign SelDTIM = '0; end ///////////////////////////////////////////////////////////////////////////////////////////// From 382ccf74a519e28dc54ea4385610bad179ecff82 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Oct 2022 15:46:53 -0500 Subject: [PATCH 17/32] Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS. --- pipelined/src/ifu/ifu.sv | 6 ++++-- pipelined/src/lsu/lsu.sv | 30 ++++++++++++++++++++---------- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2f9c6f0a1..a011a9e85 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -216,7 +216,8 @@ module ifu ( logic [1:0] CacheBusRW, BusRW; - assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; + //assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; + assign BusRW = ~IgnoreRequest & ~CacheableF & ~SelIROM ? IFURWF : '0; cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) @@ -253,7 +254,8 @@ module ifu ( logic CaptureEn; logic [31:0] FetchBuffer; logic [1:0] BusRW; - assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM}; + assign BusRW = ~IgnoreRequest & ~SelIROM ? IFURWF : '0; +// assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM}; assign IFUHSIZE = 3'b010; ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 8e7059742..18ab00b9c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -193,7 +193,7 @@ module lsu ( assign {LoadPageFaultM, StoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM; assign CacheableM = '1; - assign SelDTIM = '0; + assign SelDTIM = '0; // if no pma then always select the bus or cache. end ///////////////////////////////////////////////////////////////////////////////////////////// @@ -202,7 +202,7 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// logic [`LLEN-1:0] LSUWriteDataM, LittleEndianWriteDataM; logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; - logic [`LLEN-1:0] ReadDataWordMuxM, DTIMReadDataWordM, ReadDataWordMux2M, DCacheReadDataWordM; + logic [`LLEN-1:0] ReadDataWordMuxM, DTIMReadDataWordM, DCacheReadDataWordM; logic IgnoreRequest; assign IgnoreRequest = IgnoreRequestTLB | TrapM; @@ -212,7 +212,8 @@ module lsu ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. assign DTIMAdr = MemRWM[0] ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS - assign DTIMMemRWM = LSURWM & ~{IgnoreRequest, IgnoreRequest} & {SelDTIM, SelDTIM}; + assign DTIMMemRWM = SelDTIM & ~IgnoreRequest ? LSURWM : '0; +// assign DTIMMemRWM = LSURWM & ~{IgnoreRequest, IgnoreRequest} & {SelDTIM, SelDTIM}; dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), .Adr(DTIMAdr), .TrapM, .WriteDataM(LSUWriteDataM), @@ -235,7 +236,8 @@ module lsu ( logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; - assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM} & ~{SelDTIM, SelDTIM}; + assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; +// assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM} & ~{SelDTIM, SelDTIM}; cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( @@ -258,10 +260,17 @@ module lsu ( .SelUncachedAdr, .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); +/* -----\/----- EXCLUDED -----\/----- mux2 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`LLEN) ReadDataMux2(.d0(ReadDataWordMuxM), .d1({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s(SelDTIM), .y(ReadDataWordMux2M)); + -----/\----- EXCLUDED -----/\----- */ + + mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), + .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), + .s({SelDTIM, SelUncachedAdr}), .y(ReadDataWordMuxM)); + mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(PreHWDATA)); @@ -278,7 +287,8 @@ module lsu ( logic CaptureEn; logic [1:0] BusRW; logic [`XLEN-1:0] FetchBuffer; - assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{SelDTIM, SelDTIM}; + assign BusRW = ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; +// assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{SelDTIM, SelDTIM}; assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; @@ -288,14 +298,14 @@ module lsu ( .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); - if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMux2M); - else assign ReadDataWordMux2M = FetchBuffer[`XLEN-1:0]; + if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM); + else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0]; assign LSUHBURST = 3'b0; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; end end else begin: nobus // block: bus assign LSUHWDATA = '0; - assign ReadDataWordMux2M = DTIMReadDataWordM; + assign ReadDataWordMuxM = DTIMReadDataWordM; assign {BusStall, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM} = '0; @@ -342,10 +352,10 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// if (`BIGENDIAN_SUPPORTED) begin:endian endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); - endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMux2M), .y(LittleEndianReadDataWordM)); + endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); end else begin assign LSUWriteDataM = LittleEndianWriteDataM; - assign LittleEndianReadDataWordM = ReadDataWordMux2M; + assign LittleEndianReadDataWordM = ReadDataWordMuxM; end endmodule From 55e4911cf04b0a911404980178bf2378cbc446f0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 9 Oct 2022 03:37:27 -0700 Subject: [PATCH 18/32] fdivsqrt code cleanup --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 3 +- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 65 +++++++++++----------- 2 files changed, 33 insertions(+), 35 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 19679aa55..9af93fb37 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -55,7 +55,6 @@ module fdivsqrt( // output logic [`XLEN-1:0] RemM, ); - logic [`DIVb+3:0] NextWSN, NextWCN; logic [`DIVb+3:0] WS, WC; logic [`DIVb+3:0] X; logic [`DIVN-2:0] D; // U0.N-1 @@ -77,7 +76,7 @@ module fdivsqrt( .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, - .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, + .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .DivBusy); fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM); diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index d13d706f4..5e22be3ee 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -41,7 +41,6 @@ module fdivsqrtiter( input logic [`DIVb+3:0] X, input logic [`DIVN-2:0] Dpreproc, output logic [`DIVN-2:0] D, // U0.N-1 - output logic [`DIVb+3:0] NextWSN, NextWCN, output logic [`DIVb:0] FirstU, FirstUM, output logic [`DIVb+1:0] FirstC, output logic Firstun, @@ -58,10 +57,10 @@ module fdivsqrtiter( /* verilator lint_off UNOPTFLAT */ logic [`DIVb+3:0] WSA[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WCA[`DIVCOPIES-1:0]; // Q4.b - logic [`DIVb+3:0] WS[`DIVCOPIES-1:0]; // Q4.b - logic [`DIVb+3:0] WC[`DIVCOPIES-1:0]; // Q4.b - logic [`DIVb:0] U[`DIVCOPIES-1:0]; // U1.b - logic [`DIVb:0] UM[`DIVCOPIES-1:0];// 1.b + logic [`DIVb+3:0] WS[`DIVCOPIES:0]; // Q4.b + logic [`DIVb+3:0] WC[`DIVCOPIES:0]; // Q4.b + logic [`DIVb:0] U[`DIVCOPIES:0]; // U1.b + logic [`DIVb:0] UM[`DIVCOPIES:0];// 1.b logic [`DIVb:0] UNext[`DIVCOPIES-1:0];// U1.b logic [`DIVb:0] UMNext[`DIVCOPIES-1:0];// U1.b logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b @@ -85,25 +84,33 @@ module fdivsqrtiter( // - otherwise load WSA into the flipflop // - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection) // - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized - assign NextWSN = WSA[`DIVCOPIES-1] << `LOGR; - assign NextWCN = WCA[`DIVCOPIES-1] << `LOGR; - - // Initialize C to -1 for sqrt and -R for division - logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper; - assign initCSqrt = 2'b11; // -1 - assign initCDiv2 = 2'b10; // -2 - assign initCDiv4 = 2'b00; // -4 - assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2; - assign initC = {initCUpper, {`DIVb{1'b0}}}; - - mux2 #(`DIVb+4) wsmux(NextWSN, X, DivStartE, WSN); + + // Residual WS/SC registers/initializaiton mux + mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, DivStartE, WSN); + mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, DivStartE, WCN); flopen #(`DIVb+4) wsflop(clk, DivStartE|DivBusy, WSN, WS[0]); - mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStartE, WCN); flopen #(`DIVb+4) wcflop(clk, DivStartE|DivBusy, WCN, WC[0]); - flopen #(`DIVN-1) dflop(clk, DivStartE, Dpreproc, D); + + // UOTFC Result U and UM registers/initialization mux + // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division + assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0; + assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}}; + mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStartE, UMux); + mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStartE, UMMux); + flopen #(`DIVb+1) UReg(clk, DivStartE|DivBusy, UMux, U[0]); + flopen #(`DIVb+1) UMReg(clk, DivStartE|DivBusy, UMMux, UM[0]); + + // C register/initialization mux + // Initialize C to -1 for sqrt and -R for division + logic [1:0] initCUpper; + assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10; + assign initC = {initCUpper, {`DIVb{1'b0}}}; mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStartE, CMux); flopen #(`DIVb+2) cflop(clk, DivStartE|DivBusy, CMux, C[0]); + // Divisior register + flopen #(`DIVN-1) dflop(clk, DivStartE, Dpreproc, D); + // Divisor Selections // - choose the negitive version of what's being selected // - D is only the fraction @@ -113,6 +120,7 @@ module fdivsqrtiter( assign D2 = {2'b0, 1'b1, D, {`DIVb+2-`DIVN{1'b0}}}; end + // k=DIVCOPIES of the recurrence logic genvar i; generate for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations @@ -127,23 +135,14 @@ module fdivsqrtiter( .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end - if(i<(`DIVCOPIES-1)) begin - assign WS[i+1] = WSA[i] << `LOGR; - assign WC[i+1] = WCA[i] << `LOGR; - assign U[i+1] = UNext[i]; - assign UM[i+1] = UMNext[i]; - end + assign WS[i+1] = WSA[i] << `LOGR; + assign WC[i+1] = WCA[i] << `LOGR; + assign U[i+1] = UNext[i]; + assign UM[i+1] = UMNext[i]; end endgenerate - // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division - assign initU = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0; - assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}}; - mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStartE, UMux); - mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStartE, UMMux); - flopen #(`DIVb+1) UReg(clk, DivStartE|DivBusy, UMux, U[0]); - flopen #(`DIVb+1) UMReg(clk, DivStartE|DivBusy, UMMux, UM[0]); - + // Send values from start of cycle for postprocessing assign FirstWS = WS[0]; assign FirstWC = WC[0]; assign FirstU = U[0]; From dceb6f9034854fc3ee26a48bf367f7ed111573e2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 9 Oct 2022 04:45:45 -0700 Subject: [PATCH 19/32] Moved shift into divsqrt stage and cleaned up comments --- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 20 ++++------ pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 14 +++++-- pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 40 +++++++++++--------- 3 files changed, 42 insertions(+), 32 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index 5e22be3ee..5c067796c 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -55,8 +55,8 @@ module fdivsqrtiter( // U/UM should be 1.b so b+1 bits or b:0 // C needs to be the lenght of the final fraction 0.b so b or b-1:0 /* verilator lint_off UNOPTFLAT */ - logic [`DIVb+3:0] WSA[`DIVCOPIES-1:0]; // Q4.b - logic [`DIVb+3:0] WCA[`DIVCOPIES-1:0]; // Q4.b + logic [`DIVb+3:0] WSNext[`DIVCOPIES-1:0]; // Q4.b + logic [`DIVb+3:0] WCNext[`DIVCOPIES-1:0]; // Q4.b logic [`DIVb+3:0] WS[`DIVCOPIES:0]; // Q4.b logic [`DIVb+3:0] WC[`DIVCOPIES:0]; // Q4.b logic [`DIVb:0] U[`DIVCOPIES:0]; // U1.b @@ -78,12 +78,8 @@ module fdivsqrtiter( // Top Muxes and Registers // When start is asserted, the inputs are loaded into the divider. - // Otherwise, the divisor is retained and the partial remainder - // is fed back for the next iteration. - // - when the start signal is asserted X and 0 are loaded into WS and WC - // - otherwise load WSA into the flipflop - // - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection) - // - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized + // Otherwise, the divisor is retained and the residual and result + // are fed back for the next iteration. // Residual WS/SC registers/initializaiton mux mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, DivStartE, WSN); @@ -126,17 +122,17 @@ module fdivsqrtiter( for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations if (`RADIX == 2) begin: stage fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtM, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), + .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end else begin: stage logic j1; assign j1 = (i == 0 & ~C[0][`DIVb-1]); fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtM, .j1, - .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), + .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end - assign WS[i+1] = WSA[i] << `LOGR; - assign WC[i+1] = WCA[i] << `LOGR; + assign WS[i+1] = WSNext[i]; + assign WC[i+1] = WCNext[i]; assign U[i+1] = UNext[i]; assign UM[i+1] = UMNext[i]; end diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 987f23576..8ed1664af 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -41,7 +41,7 @@ module fdivsqrtstage2 ( output logic un, output logic [`DIVb+1:0] CNext, output logic [`DIVb:0] UNext, UMNext, - output logic [`DIVb+3:0] WSA, WCA + output logic [`DIVb+3:0] WSNext, WCNext ); /* verilator lint_on UNOPTFLAT */ @@ -49,8 +49,7 @@ module fdivsqrtstage2 ( logic up, uz; logic [`DIVb+3:0] F; logic [`DIVb+3:0] AddIn; - - assign CNext = {1'b1, C[`DIVb+1:1]}; + logic [`DIVb+3:0] WSA, WCA; // Qmient Selection logic // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un) @@ -61,8 +60,11 @@ module fdivsqrtstage2 ( // 0010 = -1 // 0001 = -2 fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un); + + // Sqrt F generatin fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F); + // Divisor multiple always_comb if (up) Dsel = DBar; else if (uz) Dsel = '0; // qz @@ -72,7 +74,13 @@ module fdivsqrtstage2 ( // WSA, WCA = WS + WC - qD assign AddIn = SqrtM ? F : Dsel; csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtM, WSA, WCA); + assign WSNext = WSA << 1; + assign WCNext = WCA << 1; + // Shift thermometer code C + assign CNext = {1'b1, C[`DIVb+1:1]}; + + // Unified On-The-Fly Converter to accumulate result fdivsqrtuotfc2 uotfc2(.up, .uz, .C(CNext), .U, .UM, .UNext, .UMNext); endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index e463762a2..e4931d4d0 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -30,7 +30,6 @@ `include "wally-config.vh" -/* verilator lint_off UNOPTFLAT */ module fdivsqrtstage4 ( input logic [`DIVN-2:0] D, input logic [`DIVb+3:0] DBar, D2, DBar2, @@ -41,9 +40,8 @@ module fdivsqrtstage4 ( input logic SqrtM, j1, output logic un, output logic [`DIVb:0] UNext, UMNext, - output logic [`DIVb+3:0] WSA, WCA + output logic [`DIVb+3:0] WSNext, WCNext ); - /* verilator lint_on UNOPTFLAT */ logic [`DIVb+3:0] Dsel; logic [3:0] udigit; @@ -51,7 +49,7 @@ module fdivsqrtstage4 ( logic [`DIVb+3:0] AddIn; logic [4:0] Smsbs; logic CarryIn; - assign CNext = {2'b11, C[`DIVb+1:2]}; + logic [`DIVb+3:0] WSA, WCA; // Digit Selection logic // u encoding: @@ -62,27 +60,35 @@ module fdivsqrtstage4 ( // 0001 = -2 assign Smsbs = U[`DIVb:`DIVb-4]; fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .udigit); + assign un = 0; // unused for radix 4 + + // F generation logic fdivsqrtfgen4 fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F); + // Divisor multiple logic always_comb - case (udigit) - 4'b1000: Dsel = DBar2; - 4'b0100: Dsel = DBar; - 4'b0000: Dsel = '0; - 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; - 4'b0001: Dsel = D2; - default: Dsel = 'x; - endcase + case (udigit) + 4'b1000: Dsel = DBar2; + 4'b0100: Dsel = DBar; + 4'b0000: Dsel = '0; + 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; + 4'b0001: Dsel = D2; + default: Dsel = 'x; + endcase - // Partial Product Generation - // WSA, WCA = WS + WC - qD + // Residual Update + // {WS, WC}}Next = (WS + WC - qD or F) << 2 assign AddIn = SqrtM ? F : Dsel; assign CarryIn = ~SqrtM & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA); - - fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext); + assign WSNext = WSA << 2; + assign WCNext = WCA << 2; - assign un = 0; // unused for radix 4 + // Shift thermometer code C + assign CNext = {2'b11, C[`DIVb+1:2]}; + + // On-the-fly converter to accumulate result + fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext); endmodule From 6092ca757a5258922ef41d2c8184dfda08f70b76 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 9 Oct 2022 04:47:44 -0700 Subject: [PATCH 20/32] New fdivsqrtqsel4cmp module based on comparators rather than table lookup --- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 15 +-- .../src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 93 +++++++++++++++++++ pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 8 +- 3 files changed, 109 insertions(+), 7 deletions(-) create mode 100644 pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index 4379724ff..73f4e4425 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -31,19 +31,18 @@ `include "wally-config.vh" module fdivsqrtqsel4 ( - input logic [`DIVN-2:0] D, + input logic [2:0] Dmsbs, input logic [4:0] Smsbs, - input logic [`DIVb+3:0] WS, WC, + input logic [7:0] WSmsbs, WCmsbs, input logic Sqrt, j1, output logic [3:0] udigit ); logic [6:0] Wmsbs; logic [7:0] PreWmsbs; - logic [2:0] Dmsbs, A; + logic [2:0] A; - assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; + assign PreWmsbs = WCmsbs + WSmsbs; assign Wmsbs = PreWmsbs[7:1]; - assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; // D = 0001.xxx... // Dmsbs = | | // W = xxxx.xxx... @@ -51,6 +50,7 @@ module fdivsqrtqsel4 ( logic [3:0] USel4[1023:0]; + // Prepopulate selection table; this is constant at compile time always_comb begin integer a, w, i, w2; for(a=0; a<8; a++) @@ -101,12 +101,15 @@ module fdivsqrtqsel4 ( endcase end end + + // Select A always_comb if (Sqrt) begin if (j1) A = 3'b101; else if (Smsbs == 5'b10000) A = 3'b111; else A = Smsbs[2:0]; end else A = Dmsbs; + + // Select quotient digit from lookup table based on A and W assign udigit = USel4[{A,Wmsbs}]; - endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv new file mode 100644 index 000000000..de4c22a18 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -0,0 +1,93 @@ +/////////////////////////////////////////// +// fdivsqrtqsel4cmp.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Comparator-based Radix 4 Quotient Digit Selection +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtqsel4cmp ( + input logic [2:0] Dmsbs, + input logic [4:0] Smsbs, + input logic [7:0] WSmsbs, WCmsbs, + input logic Sqrt, j1, + output logic [3:0] udigit +); + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] A; + + assign PreWmsbs = WCmsbs + WSmsbs; + assign Wmsbs = PreWmsbs[7:1]; + // D = 0001.xxx... + // Dmsbs = | | + // W = xxxx.xxx... + // Wmsbs = | | + + logic [6:0] mk2, mk1, mk0, mkm1; + logic [6:0] mks2[7:0], mks1[7:0]; + + // Prepopulate table of mks0 + assign mks2[0] = 12; + assign mks2[1] = 14; + assign mks2[2] = 16; + assign mks2[3] = 17; + assign mks2[4] = 18; + assign mks2[5] = 20; + assign mks2[6] = 22; + assign mks2[7] = 23; + assign mks1[0] = 4; + assign mks1[1] = 4; + assign mks1[2] = 6; + assign mks1[3] = 6; + assign mks1[4] = 6; + assign mks1[5] = 8; // is the logic any cheaper if this is a 6? + assign mks1[6] = 8; + assign mks1[7] = 8; + + // Choose A for current operation + always_comb + if (Sqrt) begin + if (j1) A = 3'b101; + else if (Smsbs == 5'b10000) A = 3'b111; + else A = Smsbs[2:0]; + end else A = Dmsbs; + + // Choose selection constants based on a + assign mk2 = mks2[A]; + assign mk1 = mks1[A]; + assign mk0 = -mks1[A]; + assign mkm1 = (A == 3'b000) ? -13 : -mks2[A]; // asymmetry in table + + // Compare residual W to selection constants to choose digit + always_comb + if ($signed(Wmsbs) >= $signed(mk2)) udigit = 4'b1000; // choose 2 + else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1 + else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0 + else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1 + else udigit = 4'b0001; // choose -2 +endmodule diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index e4931d4d0..05792293c 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -48,6 +48,8 @@ module fdivsqrtstage4 ( logic [`DIVb+3:0] F; logic [`DIVb+3:0] AddIn; logic [4:0] Smsbs; + logic [2:0] Dmsbs; + logic [7:0] WCmsbs, WSmsbs; logic CarryIn; logic [`DIVb+3:0] WSA, WCA; @@ -59,7 +61,11 @@ module fdivsqrtstage4 ( // 0010 = -1 // 0001 = -2 assign Smsbs = U[`DIVb:`DIVb-4]; - fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .udigit); + assign Dmsbs = D[`DIVN-2:`DIVN-4]; + assign WCmsbs = WC[`DIVb+3:`DIVb-4]; + assign WSmsbs = WS[`DIVb+3:`DIVb-4]; + + fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .Sqrt(SqrtM), .j1, .udigit); assign un = 0; // unused for radix 4 // F generation logic From b52f593ecb1b5d5aa59aefb215acc766871586fa Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 9 Oct 2022 16:46:48 -0500 Subject: [PATCH 21/32] Reorganized the configs. --- pipelined/config/rv32i/wally-config.vh | 18 +++++++++--------- pipelined/config/rv32ic/wally-config.vh | 14 +++++++------- pipelined/config/rv64i/wally-config.vh | 6 +++--- pipelined/config/rv64ic/wally-config.vh | 8 ++++---- pipelined/regression/regression-wally | 4 ++-- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 09c14606a..3d89efacb 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -38,11 +38,11 @@ `define IEEE754 0 // I -`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) +`define MISA (32'h00000104) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 +`define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 // Microarchitectural Features @@ -50,11 +50,11 @@ `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 // TLB configuration. Entries should be a power of 2 @@ -101,16 +101,16 @@ `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 +`define CLINT_SUPPORTED 1'b0 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 +`define GPIO_SUPPORTED 1'b0 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 +`define UART_SUPPORTED 1'b0 `define UART_BASE 34'h10000000 `define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 +`define PLIC_SUPPORTED 1'b0 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF `define SDC_SUPPORTED 1'b0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index d865623d6..ba47915de 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -37,11 +37,11 @@ // IEEE 754 compliance `define IEEE754 0 -`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 +`define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 +`define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 // Microarchitectural Features @@ -49,7 +49,7 @@ `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 @@ -103,13 +103,13 @@ `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b0 +`define GPIO_SUPPORTED 1'b1 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b0 +`define UART_SUPPORTED 1'b1 `define UART_BASE 34'h10000000 `define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b0 +`define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF `define SDC_SUPPORTED 1'b0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 05af9011f..252e5482c 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -38,11 +38,11 @@ `define IEEE754 0 // MISA RISC-V configuration per specification I -`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) +`define MISA (32'h00000104 ) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 +`define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 /// Microarchitectural Features diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index e820e57cf..0afe314bd 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -38,11 +38,11 @@ `define IEEE754 0 // MISA RISC-V configuration per specification -`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 +`define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 +`define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 // Microarchitectural Features @@ -51,7 +51,7 @@ `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 48dd7c26c..15c7a0a24 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -82,7 +82,7 @@ for test in tests32gc: grepstr="All tests ran without failures") configs.append(tc) -tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c"] +tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c", "wally32periph"] for test in tests32ic: tc = TestCase( name=test, @@ -91,7 +91,7 @@ for test in tests32ic: grepstr="All tests ran without failures") configs.append(tc) -tests32i = ["arch32i", "wally32periph"] +tests32i = ["arch32i", "imperas32i"] for test in tests32i: tc = TestCase( name=test, From 849d6d4297f1eaf76071b3ee5c8649d6fdb61db2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 10 Oct 2022 06:59:11 -0700 Subject: [PATCH 22/32] Changed SNPS license server --- setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.sh b/setup.sh index b3f9fb11e..2ae92f1bb 100755 --- a/setup.sh +++ b/setup.sh @@ -31,7 +31,7 @@ export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH # Change this export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim, or delete export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler -export SNPSLMD_LICENSE_FILE=27020@134.173.38.214 +export SNPSLMD_LICENSE_FILE=27020@134.173.38.184 # Change this to your license manager file # Imperas; put this in if you are using it #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH From a5a922d04816eda106f54c000f4e07c0f85236e7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 10 Oct 2022 07:12:37 -0700 Subject: [PATCH 23/32] Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing --- pipelined/src/lsu/subwordread.sv | 25 ++++++----------------- pipelined/src/wally/wallypipelinedcore.sv | 1 + 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index 8d5ed4de5..583bcf274 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -85,19 +85,10 @@ module subwordread always_comb case(Funct3M) 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb - 3'b001: if(`ZFH_SUPPORTED) - ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh - else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh - 3'b010: if(`F_SUPPORTED) - ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw - else ReadDataM = {{`LLEN-32{WordM[31]}}, WordM[31:0]}; // lw - 3'b011: if(`D_SUPPORTED) - ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld - else ReadDataM = {{`LLEN-64{DblWordM[63]}}, DblWordM[63:0]}; // ld/fld - 3'b100: if(`Q_SUPPORTED) - ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - else - ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b001: ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh + 3'b010: ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw + 3'b011: ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld + 3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu 3'b110: ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]}; // lwu default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen @@ -124,12 +115,8 @@ module subwordread always_comb case(Funct3M) 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb - 3'b001: if(`ZFH_SUPPORTED) - ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh - else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh - 3'b010: if(`F_SUPPORTED) - ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw - else ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; // lw + 3'b001: ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh + 3'b010: ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw 3'b011: ReadDataM = ReadDataWordMuxM; // fld 3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 0f61f452d..277ca4266 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -414,5 +414,6 @@ module wallypipelinedcore ( assign FDivBusyE = 0; assign IllegalFPUInstrM = 1; assign SetFflagsM = 0; + assign FpLoadStoreM = 0; end endmodule From e4c5754b3ae998bd9cf3da80958398d27b39dab8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 10 Oct 2022 09:10:55 -0700 Subject: [PATCH 24/32] Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width --- pipelined/config/rv64fp/wally-config.vh | 147 ------------------------ pipelined/config/rv64i/wally-config.vh | 46 ++++---- pipelined/config/rv64ic/wally-config.vh | 146 ----------------------- pipelined/config/shared/wally-shared.vh | 11 +- pipelined/regression/lint-wally | 2 +- pipelined/regression/regression-wally | 9 ++ pipelined/src/ifu/irom.sv | 8 +- pipelined/src/lsu/lsu.sv | 4 +- 8 files changed, 50 insertions(+), 323 deletions(-) delete mode 100644 pipelined/config/rv64fp/wally-config.vh delete mode 100644 pipelined/config/rv64ic/wally-config.vh diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh deleted file mode 100644 index b708bbb59..000000000 --- a/pipelined/config/rv64fp/wally-config.vh +++ /dev/null @@ -1,147 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 -`define DESIGN_COMPILER 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -// MISA RISC-V configuration per specification -// ZYXWVUTSRQPONMLKJIHGFEDCBA -`define MISA 32'b0000000000101000001000100101101 -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 - -/// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 - -// LSU microarchitectural Features -`define BUS 1 -`define DCACHE 1 -`define ICACHE 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 64 - -// Address space -`define RESET_VECTOR 64'h0000000080000000 - -// Bus Interface width -`define AHBW 64 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h00001FFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h00001FFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h7FFFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 -`define BPRED_SIZE 10 - -`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 252e5482c..098755cd2 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -37,30 +37,30 @@ // IEEE 754 compliance `define IEEE754 0 -// MISA RISC-V configuration per specification I -`define MISA (32'h00000104 ) -`define ZICSR_SUPPORTED 1 +// MISA RISC-V configuration per specification +`define MISA (32'h00000104) +`define ZICSR_SUPPORTED 0 `define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 -/// Microarchitectural Features +// Microarchitectural Features `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 1 -`define DCACHE 1 -`define ICACHE 1 -`define VIRTMEM_SUPPORTED 1 +`define BUS 0 +`define DCACHE 0 +`define ICACHE 0 +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 // TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 +`define ITLB_ENTRIES 0 +`define DTLB_ENTRIES 0 // Cache configuration. Sizes should be a power of two // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines @@ -76,13 +76,13 @@ `define DIV_BITSPERCYCLE 4 // Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 64 +`define PMP_ENTRIES 0 // Address space `define RESET_VECTOR 64'h0000000080000000 // Bus Interface width -`define AHBW 64 +`define AHBW (`XLEN) // WFI Timeout Wait `define WFI_TIMEOUT_BIT 16 @@ -92,31 +92,31 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b0 +`define DTIM_SUPPORTED 1'b1 `define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h00001FFF -`define IROM_SUPPORTED 1'b0 +`define DTIM_RANGE 56'h007FFFFF +`define IROM_SUPPORTED 1'b1 `define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h00001FFF -`define BOOTROM_SUPPORTED 1'b1 +`define IROM_RANGE 56'h007FFFFF +`define BOOTROM_SUPPORTED 1'b0 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_SUPPORTED 1'b0 `define UNCORE_RAM_BASE 56'h80000000 `define UNCORE_RAM_RANGE 56'h7FFFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 +`define CLINT_SUPPORTED 1'b0 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 +`define GPIO_SUPPORTED 1'b0 `define GPIO_BASE 56'h10060000 `define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 +`define UART_SUPPORTED 1'b0 `define UART_BASE 56'h10000000 `define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 +`define PLIC_SUPPORTED 1'b0 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF `define SDC_SUPPORTED 1'b0 @@ -138,7 +138,7 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define BPRED_ENABLED 1 +`define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh deleted file mode 100644 index 0afe314bd..000000000 --- a/pipelined/config/rv64ic/wally-config.vh +++ /dev/null @@ -1,146 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 -`define DESIGN_COMPILER 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -// MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 - -// LSU microarchitectural Features -`define BUS 1 -`define DCACHE 0 -`define ICACHE 0 -`define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 0 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 64'h0000000080000000 - -// Bus Interface width -`define AHBW 64 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b1 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h007FFFFF -`define IROM_SUPPORTED 1'b1 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h007FFFFF -`define BOOTROM_SUPPORTED 1'b0 -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h7FFFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 -`define BPRED_SIZE 10 - -`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index cd5bb05e3..b4fc2ceab 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -73,11 +73,18 @@ `define H_FMT 2'd2 // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits +`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS) +/* Delete once tested dh 10/10/22 + `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) `define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) `define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ // Floating point constants needed for FPU paramerterization `define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 750486c4e..705fbd61e 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic rv64fpquad; do +for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 15c7a0a24..f3896775c 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -73,6 +73,15 @@ for test in tests64gc: grepstr="All tests ran without failures") configs.append(tc) +tests64i = ["arch64i", "imperas64i"] +for test in tests64i: + tc = TestCase( + name=test, + variant="rv64i", + cmd="vsim > {} -c < Date: Mon, 10 Oct 2022 10:22:12 -0700 Subject: [PATCH 25/32] Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU --- pipelined/regression/regression-wally | 4 ++-- pipelined/src/lsu/lsu.sv | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index f3896775c..5318a0f76 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -73,7 +73,7 @@ for test in tests64gc: grepstr="All tests ran without failures") configs.append(tc) -tests64i = ["arch64i", "imperas64i"] +tests64i = ["arch64i"] for test in tests64i: tc = TestCase( name=test, @@ -100,7 +100,7 @@ for test in tests32ic: grepstr="All tests ran without failures") configs.append(tc) -tests32i = ["arch32i", "imperas32i"] +tests32i = ["arch32i"] for test in tests32i: tc = TestCase( name=test, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f7fdcca1d..06f6446b4 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -154,7 +154,6 @@ module lsu ( assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; // MMU and Misalignment fault logic required if privileged unit exists - // *** DH: This is too strong a requirement. Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED if(`ZICSR_SUPPORTED == 1) begin : dmmu logic DisableTranslation; assign DisableTranslation = SelHPTW | FlushDCacheM; From 403daecc8eb4bcc8a5d1422e3059e240f2bacb72 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 11 Oct 2022 10:47:13 -0500 Subject: [PATCH 26/32] Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. The defaults are used for synthesis. rv64i and rv32i: DTIM 2KiB, IROM 2KiB rv32ic: DTIM 4KiB, IROM 16KiB Regression tests require 8MiB or larger so modelsim overrides. --- pipelined/config/rv32i/wally-config.vh | 6 +++--- pipelined/config/rv32ic/wally-config.vh | 4 ++-- pipelined/config/rv64i/wally-config.vh | 4 ++-- pipelined/regression/wally-pipelined-batch.do | 2 +- pipelined/regression/wally-pipelined.do | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 3d89efacb..03a58d1a9 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -88,11 +88,11 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits `define DTIM_SUPPORTED 1'b1 `define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h07FFFFFF +`define DTIM_RANGE 34'h000007FF `define IROM_SUPPORTED 1'b1 `define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h07FFFFFF -`define BOOTROM_SUPPORTED 1'b1 +`define IROM_RANGE 34'h000007FF +`define BOOTROM_SUPPORTED 1'b0 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF `define UNCORE_RAM_SUPPORTED 1'b0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index ba47915de..752425782 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -87,10 +87,10 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits `define DTIM_SUPPORTED 1'b1 `define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h007FFFFF +`define DTIM_RANGE 34'h00000FFF `define IROM_SUPPORTED 1'b1 `define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h007FFFFF +`define IROM_RANGE 34'h00003FFF `define BOOTROM_SUPPORTED 1'b0 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 098755cd2..b3b547cc9 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -94,10 +94,10 @@ // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define DTIM_SUPPORTED 1'b1 `define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h007FFFFF +`define DTIM_RANGE 56'h000007FF `define IROM_SUPPORTED 1'b1 `define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h007FFFFF +`define IROM_RANGE 56'h000007FF `define BOOTROM_SUPPORTED 1'b0 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 1e70e2348..a31b753d5 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -76,7 +76,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { run -all # power off -r /dut/core/* } else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 +define+DTIM_RANGE=8388607 +define+IROM_RANGE=8388607 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index fe17bd57e..9e8477303 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -79,7 +79,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { if {$2 eq "ahb"} { vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 } else { - vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+DTIM_RANGE=8388607 +define+IROM_RANGE=8388607 } vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt From a5c15fd80139f1b30ee8269eba1866ba64926923 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 11 Oct 2022 11:35:40 -0500 Subject: [PATCH 27/32] Fixed first problem with the rv64i IROM. --- pipelined/src/ifu/irom.sv | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index 981eadb08..af262ba8b 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -42,6 +42,11 @@ module irom( rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull)); if (`XLEN == 32) assign ReadData = ReadDataFull; - else assign ReadData = Adr[OFFSET] ? ReadDataFull[63:32] : ReadDataFull[31:0]; + // have to delay Ardr[OFFSET-1] by 1 cycle + else begin + logic AdrD; + flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD); + assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0]; + end endmodule From b2f71b8255d3b1957cb2cc51637a2dfb92f1d7fc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 11 Oct 2022 14:05:20 -0500 Subject: [PATCH 28/32] Modified LSU to support DTIM without CSRs. --- pipelined/src/lsu/lsu.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 06f6446b4..2af5851ee 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -192,7 +192,8 @@ module lsu ( assign {LoadPageFaultM, StoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM[`PA_BITS-1:0]; assign CacheableM = '1; - assign SelDTIM = '0; // if no pma then always select the bus or cache. + assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no pma then select dtim if there is a DTIM. If there is + // a bus then this is always 0. Cannot have both without PMA. end ///////////////////////////////////////////////////////////////////////////////////////////// From f711eb0bcfdb234d19d8af3a0b344c63467b6835 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 11 Oct 2022 23:08:02 +0000 Subject: [PATCH 29/32] quick fix to endianness wapping 64 bit reads in 32 bit confgs --- pipelined/src/lsu/lsu.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2af5851ee..2bab17275 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -350,9 +350,13 @@ module lsu ( // hart works little-endian internally // swap the bytes when read from big-endian memory ///////////////////////////////////////////////////////////////////////////////////////////// + if (`BIGENDIAN_SUPPORTED) begin:endian + logic [`LLEN-1:0] ReadDataWordMuxSwapM; // *** swap the top and bottom XLEN bits based on endianness // Ross doesn't like this + if (`LLEN == 2*`XLEN) assign ReadDataWordMuxSwapM = BigEndianM ? {ReadDataWordMuxM[`XLEN-1:0], ReadDataWordMuxM[`LLEN-1:`XLEN]} : ReadDataWordMuxM; + else assign ReadDataWordMuxSwapM = ReadDataWordMuxM; endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); - endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); + endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxSwapM), .y(LittleEndianReadDataWordM)); end else begin assign LSUWriteDataM = LittleEndianWriteDataM; assign LittleEndianReadDataWordM = ReadDataWordMuxM; From 12a6a9f83bb4cb19eed33c16111d45f5505dba08 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 12 Oct 2022 11:33:10 -0500 Subject: [PATCH 30/32] Actually fixed the bus width issue coming out of the cache. The root cause is the ahb bus width can be different from LLEN. If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well. Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN. --- pipelined/src/lsu/lsu.sv | 42 ++++++++++++++------------------ pipelined/src/lsu/subwordread.sv | 2 +- 2 files changed, 19 insertions(+), 25 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2bab17275..253841826 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -213,7 +213,6 @@ module lsu ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. assign DTIMAdr = MemRWM[0] ? IEUAdrExtM[`PA_BITS-1:0] : IEUAdrExtE[`PA_BITS-1:0]; // zero extend or contract to PA_BITS assign DTIMMemRWM = SelDTIM & ~IgnoreRequest ? LSURWM : '0; -// assign DTIMMemRWM = LSURWM & ~{IgnoreRequest, IgnoreRequest} & {SelDTIM, SelDTIM}; dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), .Adr(DTIMAdr), .TrapM, .WriteDataM(LSUWriteDataM), @@ -221,15 +220,17 @@ module lsu ( end else begin end if (`BUS) begin : bus - localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; - localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1; + localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1; + localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1; + localparam integer AHBWWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; + localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(AHBWWORDSPERLINE) : 1; if(`DCACHE) begin : dcache localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; - logic [LOGBWPL-1:0] WordCount; + logic [AHBWLOGBWPL-1:0] WordCount; logic SelUncachedAdr, DCacheBusAck; logic SelBusWord; logic [`XLEN-1:0] PreHWDATA; //*** change name @@ -237,20 +238,19 @@ module lsu ( logic [1:0] CacheBusRW, BusRW; assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; -// assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM} & ~{SelDTIM, SelDTIM}; cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( + .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), - .ByteMask(ByteMaskM), .WordCount, + .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM), .SelReplay, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) ahbcacheinterface( + ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .HRDATA, .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), @@ -260,18 +260,18 @@ module lsu ( .SelUncachedAdr, .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); -/* -----\/----- EXCLUDED -----\/----- - mux2 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), - .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`LLEN) ReadDataMux2(.d0(ReadDataWordMuxM), .d1({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), - .s(SelDTIM), .y(ReadDataWordMux2M)); - -----/\----- EXCLUDED -----/\----- */ - mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s({SelDTIM, SelUncachedAdr}), .y(ReadDataWordMuxM)); - - mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), + + + + // **** need to generalize + logic [`AHBW-1:0] DCacheReadDataWordAHB; + if(`LLEN > `AHBW) begin + assign DCacheReadDataWordAHB = WordCount[0] ? DCacheReadDataWordM[2*`AHBW-1:`AHBW] : DCacheReadDataWordM[`AHBW-1:0]; + end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; + mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), .s(SelUncachedAdr), .y(PreHWDATA)); flopen #(`XLEN) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN @@ -329,9 +329,6 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// // Subword Accesses ///////////////////////////////////////////////////////////////////////////////////////////// - // *** Ross Thompson: I think swr needs to be modified to support bigendian. Both the subword - // selected and the sign extension are probably wrong. I think it should be an invertion of - // the address bits and a different bit selected for extension. subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM); @@ -352,11 +349,8 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// if (`BIGENDIAN_SUPPORTED) begin:endian - logic [`LLEN-1:0] ReadDataWordMuxSwapM; // *** swap the top and bottom XLEN bits based on endianness // Ross doesn't like this - if (`LLEN == 2*`XLEN) assign ReadDataWordMuxSwapM = BigEndianM ? {ReadDataWordMuxM[`XLEN-1:0], ReadDataWordMuxM[`LLEN-1:`XLEN]} : ReadDataWordMuxM; - else assign ReadDataWordMuxSwapM = ReadDataWordMuxM; endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); - endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxSwapM), .y(LittleEndianReadDataWordM)); + endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); end else begin assign LSUWriteDataM = LittleEndianWriteDataM; assign LittleEndianReadDataWordM = ReadDataWordMuxM; diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index 583bcf274..610345745 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -47,7 +47,7 @@ module subwordread // Funct3M[1:0] is the size of the memory access. assign PAdrSwap = PAdrM ^ {3{BigEndianM}}; - if (`XLEN == 64) begin:swrmux + if (`LLEN == 64) begin:swrmux // ByteMe mux always_comb case(PAdrSwap[2:0]) From fccaad7f3fadcb7f3214d242adf62c6789d60431 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 12 Oct 2022 12:06:15 -0500 Subject: [PATCH 31/32] Fixed LSU to correctly handle the difference between LLEN and AHBW. --- pipelined/src/lsu/lsu.sv | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 253841826..65ca32d4f 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -264,24 +264,28 @@ module lsu ( .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s({SelDTIM, SelUncachedAdr}), .y(ReadDataWordMuxM)); - - - // **** need to generalize + // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. logic [`AHBW-1:0] DCacheReadDataWordAHB; - if(`LLEN > `AHBW) begin - assign DCacheReadDataWordAHB = WordCount[0] ? DCacheReadDataWordM[2*`AHBW-1:`AHBW] : DCacheReadDataWordM[`AHBW-1:0]; + localparam integer LLENPOVERAHBW = `LLEN / `AHBW; + if(LLENPOVERAHBW > 1) begin + logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + genvar index; + for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux + assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; + end + assign DCacheReadDataWordAHB = AHBWordSets[WordCount[$clog2(LLENPOVERAHBW)-1:0]]; end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), .s(SelUncachedAdr), .y(PreHWDATA)); - flopen #(`XLEN) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`AHBW) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec - // *** bummer need a second byte mask for bus as it is XLEN rather than LLEN. + // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - logic [`XLEN/8-1:0] BusByteMaskM; - swbytemask #(`XLEN) busswbytemask(.Size(LSUHSIZE), .Adr(PAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM)); + logic [`AHBW/8-1:0] BusByteMaskM; + swbytemask #(`AHBW) busswbytemask(.Size(LSUHSIZE), .Adr(PAdrM[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); - flop #(`XLEN/8) HWSTRBReg(clk, BusByteMaskM[`XLEN/8-1:0], LSUHWSTRB); + flop #(`ABHW/8) HWSTRBReg(clk, BusByteMaskM[`AHBW/8-1:0], LSUHWSTRB); end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn; From 47915421c27339e900ac824f5ce1d866a7aa6c47 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 13 Oct 2022 11:11:36 -0500 Subject: [PATCH 32/32] Fixed uncached read bug introduced by yesterday's changes. --- pipelined/regression/wave.do | 482 +++++++++++++++++------------------ pipelined/src/lsu/lsu.sv | 8 +- 2 files changed, 235 insertions(+), 255 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 93db10362..b363d0d1a 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -169,226 +169,226 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -expand -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount -add wave -noupdate -expand -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURSTD -add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS -add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR -add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST -add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY -add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/HRDATA -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/HRDATA -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB -add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA -add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESP -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDR -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWDATA -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITE -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZE -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HPROT -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/WordCount -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelEvict -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelBusWord -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM +add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURSTD +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA +add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/WordCount +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelEvict +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelBusWord +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim @@ -408,6 +408,14 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL @@ -554,38 +562,8 @@ add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/VPN add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/TLBWrite add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PTE add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/addr} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/din} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/ce} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/dout} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CPUBusy -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ReadTag} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ce} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/RAdr} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/PAdr} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/clk} -add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheRW -add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheHit -add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/DoRead -add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/DoAnyHit -add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/DoAnyMiss -add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CPUBusy -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/clk} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ce} -add wave -noupdate -radix unsigned {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/addr} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} -add wave -noupdate {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/Valid} -add wave -noupdate /testbench/dut/core/priv/priv/InterruptM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {200566 ns} 0} {{Cursor 3} {190821 ns} 1} {{Cursor 4} {378225 ns} 1} +WaveRestoreCursors {{Cursor 2} {6185 ns} 0} {{Cursor 3} {190821 ns} 1} {{Cursor 4} {378225 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -601,4 +579,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {200403 ns} {200739 ns} +WaveRestoreZoom {6085 ns} {6317 ns} diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 65ca32d4f..d7bfa9d11 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -236,6 +236,7 @@ module lsu ( logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; + localparam integer LLENPOVERAHBW = `LLEN / `AHBW; assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0; @@ -260,13 +261,14 @@ module lsu ( .SelUncachedAdr, .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); - mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), + // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times. + // DTIMReadDataWordM should be increased to LLEN. + mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}), .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s({SelDTIM, SelUncachedAdr}), .y(ReadDataWordMuxM)); // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. logic [`AHBW-1:0] DCacheReadDataWordAHB; - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; if(LLENPOVERAHBW > 1) begin logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; @@ -285,7 +287,7 @@ module lsu ( logic [`AHBW/8-1:0] BusByteMaskM; swbytemask #(`AHBW) busswbytemask(.Size(LSUHSIZE), .Adr(PAdrM[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); - flop #(`ABHW/8) HWSTRBReg(clk, BusByteMaskM[`AHBW/8-1:0], LSUHWSTRB); + flop #(`AHBW/8) HWSTRBReg(clk, BusByteMaskM[`AHBW/8-1:0], LSUHWSTRB); end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn;