From d89d595cb4398de2e306c3002b7c69558af13edb Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 22 Jan 2025 04:34:53 -0800 Subject: [PATCH 1/4] Cleaned up tracer parameters --- testbench/common/wallyTracer.sv | 37 ++++++++++++++++----------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 093b72de2..468e53d40 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -2,6 +2,8 @@ // wallyTracer.sv // // A component of the Wally configurable RISC-V project. +// Implements a RISC-V Verification Interface (RVVI) +// to support functional coverage and lockstep simulation. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // @@ -20,19 +22,16 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -`define NUM_REGS 32 -`define NUM_CSRS 4096 - `define STD_LOG 0 `define PRINT_PC_INSTR 0 `define PRINT_MOST 0 `define PRINT_ALL 0 `define PRINT_CSRS 0 - module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); - localparam NUMREGS = P.E_SUPPORTED ? 16 : 32; + localparam NUM_REGS = P.E_SUPPORTED ? 16 : 32; + localparam NUM_CSRS = 4096; // wally specific signals logic reset; @@ -50,17 +49,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic TrapM, TrapW; logic HaltM, HaltW; logic [1:0] PrivilegeModeW; - logic [P.XLEN-1:0] rf[NUMREGS]; - logic [NUMREGS-1:0] rf_wb; + logic [P.XLEN-1:0] rf[NUM_REGS]; + logic [NUM_REGS-1:0] rf_wb; logic [4:0] rf_a3; logic rf_we3; logic [P.FLEN-1:0] frf[32]; - logic [`NUM_REGS-1:0] frf_wb; + logic [NUM_REGS-1:0] frf_wb; logic [4:0] frf_a4; logic frf_we4; logic [P.XLEN-1:0] CSRArray [4095:0]; logic [P.XLEN-1:0] CSRArrayOld [4095:0]; - logic [`NUM_CSRS-1:0] CSR_W; + logic [NUM_CSRS-1:0] CSR_W; logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; logic wfiM; @@ -314,7 +313,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); genvar index; assign rf[0] = 0; - for(index = 1; index < NUMREGS; index += 1) + for(index = 1; index < NUM_REGS; index += 1) assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3; @@ -329,12 +328,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); if (P.F_SUPPORTED) begin assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4; assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; - for(index = 0; index < NUMREGS; index += 1) + for(index = 0; index < NUM_REGS; index += 1) assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index]; end else begin assign frf_a4 = '0; assign frf_we4 = 0; - for(index = 0; index < NUMREGS; index += 1) + for(index = 0; index < NUM_REGS; index += 1) assign frf[index] = '0; end @@ -420,7 +419,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); ~FlushE ? PCD : ~FlushD ? PCF : PCNextF; - for(index = 0; index < `NUM_REGS; index += 1) begin + for(index = 0; index < NUM_REGS; index += 1) begin assign rvvi.x_wdata[0][0][index] = rf[index]; assign rvvi.x_wb[0][0][index] = rf_wb[index]; assign rvvi.f_wdata[0][0][index] = frf[index]; @@ -744,18 +743,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); if(valid) begin if(`STD_LOG) begin $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName); - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin if(rvvi.x_wb[0][0][index2]) begin $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]); end end end - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin if(rvvi.f_wb[0][0][index2]) begin $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]); end end - for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin + for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin if(rvvi.csr_wb[0][0][index2]) begin $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]); end @@ -769,15 +768,15 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); else if(`PRINT_ALL) begin $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); end - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); end end if (`PRINT_CSRS) begin - for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin + for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin if(CSR_W[index2]) begin $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); end From f160b9c7fb4be206a52f289f459bf37361bca1ef Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 28 Jan 2025 23:58:44 -0800 Subject: [PATCH 2/4] Regression directory creation fix --- bin/regression-wally | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 4ec41bf19..9291faabc 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -479,12 +479,13 @@ def makeDirs(sims): for sim in sims: dirs = [f"{regressionDir}/{sim}/wkdir", f"{regressionDir}/{sim}/logs"] for d in dirs: - shutil.rmtree(d) + shutil.rmtree(d, ignore_errors=True) os.makedirs(d, exist_ok=True) def main(args): sims, coverStr, TIMEOUT_DUR = process_args(args) + makeDirs(sims) configs = selectTests(args, sims, coverStr) # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system From 94e83ccf1fff0b3faa9ad82c1c13c2072b9689f1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Jan 2025 06:40:15 -0800 Subject: [PATCH 3/4] Removed obsolete testbench/coverage --- testbench/coverage/test_fencei_coverage.svh | 25 ---- .../coverage/test_fencei_coverage_init.svh | 4 - testbench/coverage/test_pmp_coverage.sv | 108 ------------------ 3 files changed, 137 deletions(-) delete mode 100644 testbench/coverage/test_fencei_coverage.svh delete mode 100644 testbench/coverage/test_fencei_coverage_init.svh delete mode 100644 testbench/coverage/test_pmp_coverage.sv diff --git a/testbench/coverage/test_fencei_coverage.svh b/testbench/coverage/test_fencei_coverage.svh deleted file mode 100644 index bb492b1cb..000000000 --- a/testbench/coverage/test_fencei_coverage.svh +++ /dev/null @@ -1,25 +0,0 @@ -typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t; - -covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins); - option.per_instance = 1; - option.comment = "Fence.I"; - - cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) { - option.comment = "Number of times instruction is executed"; - bins count[] = {1}; - } -endgroup - -function void test_fencei_sample(int hart, int issue); - test_ins_rv64i_t ins; - - case (traceDataQ[hart][issue][0].inst_name) - "fenci" : begin - ins = new(hart, issue, traceDataQ); - test_fencei_cg.sample(ins); - end - endcase - -endfunction - - diff --git a/testbench/coverage/test_fencei_coverage_init.svh b/testbench/coverage/test_fencei_coverage_init.svh deleted file mode 100644 index c07507d43..000000000 --- a/testbench/coverage/test_fencei_coverage_init.svh +++ /dev/null @@ -1,4 +0,0 @@ -test_fencei_cg = new(); test_fencei_cg.set_inst_name("obj_fencei"); - -// test_fencei_cg = new(); -//test_fencei_cg.set_inst_name("obj_fencei"); diff --git a/testbench/coverage/test_pmp_coverage.sv b/testbench/coverage/test_pmp_coverage.sv deleted file mode 100644 index 2c1cbbfaa..000000000 --- a/testbench/coverage/test_pmp_coverage.sv +++ /dev/null @@ -1,108 +0,0 @@ -module test_pmp_coverage import cvw::*; #(parameter cvw_t P) (input clk); - -// Ensure the covergroup is defined correctly -covergroup cg_priv_mode @(posedge clk); - coverpoint dut.core.ifu.PrivilegeModeW { - bins user = {2'b00}; - bins superv = {2'b01}; - bins hyperv = {2'b10}; - bins mach = {2'b11}; - } -endgroup - -covergroup cg_PMPConfig @(posedge clk); - coverpoint dut.core.ifu.PMPCFG_ARRAY_REGW[0][0] { - bins ones = {1}; - bins zeros = {0}; - } -endgroup - - -function bit [1:0] getPMPConfigSlice(int index); - return dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[index][4:3]; -endfunction - -//if (P.PMP_ENTRIES > 0) begin : pmp - covergroup cg_pmpcfg_mode @(posedge clk); - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[0][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[1][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[2][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[3][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[4][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[5][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[6][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - - coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[7][4:3] { - bins off = {2'b00}; - bins tor = {2'b01}; - bins na4 = {2'b10}; - bins napot = {2'b11}; - } - endgroup -//end - - -// Ensure that the instantiation and sampling of covergroups are within the correct procedural context -initial begin - cg_priv_mode privmodeCG = new(); // Instantiate the privilege mode covergroup - cg_PMPConfig pmpconfigCG = new(); // Instantiate the PMP config covergroup - cg_pmpcfg_mode pmpcfgmodeCG = new(); - - forever begin - @(posedge clk) begin - privmodeCG.sample(); // Sample the privilege mode covergroup - pmpconfigCG.sample(); // Sample the PMP config covergroupi - pmpcfgmodeCG.sample(); - end - end -end - - -endmodule - - - - - From 2cccf4ab21884916c7e71cb74787e2e12f722255 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Jan 2025 07:32:27 -0800 Subject: [PATCH 4/4] fixed wallyTracer to have 32 FP registers independent of E --- testbench/common/wallyTracer.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 468e53d40..6ec35215d 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -54,7 +54,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [4:0] rf_a3; logic rf_we3; logic [P.FLEN-1:0] frf[32]; - logic [NUM_REGS-1:0] frf_wb; + logic [31:0] frf_wb; logic [4:0] frf_a4; logic frf_we4; logic [P.XLEN-1:0] CSRArray [4095:0]; @@ -314,7 +314,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); genvar index; assign rf[0] = 0; for(index = 1; index < NUM_REGS; index += 1) - assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; + assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3; assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3; @@ -328,12 +328,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); if (P.F_SUPPORTED) begin assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4; assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; - for(index = 0; index < NUM_REGS; index += 1) + for(index = 0; index < 32; index += 1) assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index]; end else begin assign frf_a4 = '0; assign frf_we4 = 0; - for(index = 0; index < NUM_REGS; index += 1) + for(index = 0; index < 32; index += 1) assign frf[index] = '0; end @@ -422,6 +422,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); for(index = 0; index < NUM_REGS; index += 1) begin assign rvvi.x_wdata[0][0][index] = rf[index]; assign rvvi.x_wb[0][0][index] = rf_wb[index]; + end + for(index = 0; index < 32; index += 1) begin assign rvvi.f_wdata[0][0][index] = frf[index]; assign rvvi.f_wb[0][0][index] = frf_wb[index]; end @@ -749,7 +751,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end end end - for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin + for(index2 = 0; index2 < 32; index2 += 1) begin if(rvvi.f_wb[0][0][index2]) begin $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]); end @@ -771,7 +773,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); end - for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin + for(index2 = 0; index2 < 32; index2 += 1) begin $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); end end