Merge branch 'main' of github.com:ross144/cvw

This commit is contained in:
Ross Thompson 2023-04-06 15:33:24 -05:00
commit a0471dd8bd

View File

@ -68,6 +68,8 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// READ first SRAM model // READ first SRAM model
// *************************************************************************** // ***************************************************************************
end else begin: ram end else begin: ram
// *** Vivado is not implementing this as block ram for some reason.
// The version with byte write enables it correctly infers block ram.
integer i; integer i;
// Read // Read
@ -82,7 +84,6 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
// Therefore these always blocks use the older always @(posedge clk) // Therefore these always blocks use the older always @(posedge clk)
if(WIDTH >= 8)
always @(posedge clk) always @(posedge clk)
// coverage off // coverage off
// ce only goes low when cachefsm is in READY state and Flush is asserted. // ce only goes low when cachefsm is in READY state and Flush is asserted.
@ -92,5 +93,4 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// coverage on // coverage on
RAM[addr] <= #1 din; RAM[addr] <= #1 din;
end end
endmodule endmodule