Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

This commit is contained in:
Ross Thompson 2021-12-20 23:27:46 -06:00
commit a02ac78907
4 changed files with 33 additions and 31 deletions

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@ -1,24 +1,23 @@
make all: all:
# move these parts into compiling archtest separtately install
# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F compile
# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D regression
# sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
# sed -i 's/--isa=rv64i /--isa=64id/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include # install copies over the Makefile.include from riscv-isa-sim
# if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi # And corrects the TARGETDIR path and the RISCV_PREFIXZ
# cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
# make -C addins/riscv-isa-sim/build install:
# sudo make install -C addins/riscv-isa-sim/build cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
# cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
# update with path including $RISCV_TOOLS echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
# separate into make tests and make regression
cp $RISCV/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ compile:
sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= $RISCV/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
make -C addins/riscv-arch-test make -C addins/riscv-arch-test
make -C addins/riscv-arch-test XLEN=32 make -C addins/riscv-arch-test XLEN=32
cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf
regression:
make -C wally-pipelined/regression make -C wally-pipelined/regression

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@ -10,17 +10,23 @@ echo "Executing wally-setup.sh"
export RISCV=/opt/riscv # change this if you installed the tools in a different location export RISCV=/opt/riscv # change this if you installed the tools in a different location
# Tools # Tools
export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH # GCC tools # GCCZ
export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory
export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH
export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH # GCC tools
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # *** is this the right license server now # Spike
export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
export PATH=$RISCV/bin:$PATH
# exe2memfile
export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory
# Verilator
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
# ModelSim/Questa (vsim)
export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
# Imperas; *** remove if not using # Imperas; *** remove if not using
PATH=/cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:/cad/riscv/imperas-riscv-tests/riscv-ovpsim/bin/Liux64:$PATH # *** maybe take this out based on Imperas export PATH=/cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:/cad/riscv/imperas-riscv-tests/riscv-ovpsim/bin/Liux64:$PATH # *** maybe take this out based on Imperas
export LD_LIBRARY_PATH=/cad/imperas/Imperas.20200630/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas export LD_LIBRARY_PATH=/cad/imperas/Imperas.20200630/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
IMPERAS_HOME=/cad/imperas/Imperas.20200630 export IMPERAS_HOME=/cad/imperas/Imperas.20200630
source $IMPERAS_HOME/bin/setup.sh source $IMPERAS_HOME/bin/setup.sh
setupImperas $IMPERAS_HOME setupImperas $IMPERAS_HOME

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@ -49,6 +49,5 @@ module privdec (
assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions
// *** initially, wfi and sfencevma are nop // *** initially, wfi is nop
// *** zfenci extension?
endmodule endmodule

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@ -144,10 +144,8 @@ module privileged (
/////////////////////////////////////////// ///////////////////////////////////////////
// decode privileged instructions // decode privileged instructions
/////////////////////////////////////////// ///////////////////////////////////////////
//privdec pmd(.InstrM(InstrM[31:20]),.*);
privdec pmd(.InstrM(InstrM[31:20]), privdec pmd(.InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
.PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,