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Updated header for LSU.
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///////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// Written: David_Harris@hmc.edu, ross1728@gmail.com
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// Created: 9 January 2021
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// Modified: 11 January 2023
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//
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// Purpose: Load/Store Unit
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// Top level of the memory-stage core logic
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@ -24,7 +25,7 @@
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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// committed means the memory operation in flight cannot be interrupted.
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// chap 5 handling faults to memory by delaying writes to memory stage.
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