From 4729a72167b9f3aed4dbd49cd5a6dff73e120a96 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 18 Jul 2021 20:40:49 -0400 Subject: [PATCH 1/2] Updated FMA1 with parameterized size --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- wally-pipelined/src/fpu/fma.sv | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 44a90e1c2..3235c6233 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF +`define TIM_RANGE 56'h007FFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv index 9ef187df8..9c53194db 100644 --- a/wally-pipelined/src/fpu/fma.sv +++ b/wally-pipelined/src/fpu/fma.sv @@ -89,15 +89,15 @@ module fma1( input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) input logic FmtE, // precision 1 = double 0 = single output logic [2*`NF+1:0] ProdManE, // 1.X frac * 1.Y frac in U(2.2Nf) format - output logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in *** format + output logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1) output logic [`NE+1:0] ProdExpE, // X exponent + Y exponent - bias in B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign output logic AddendStickyE, // sticky bit that is calculated during alignment output logic KillProdE // set the product to zero before addition if the product is too small to matter ); logic [`NE+1:0] AlignCnt; // how far to shift the addend to align with the product in Q(NE+2.0) format *** is this enough bits? - logic [4*`NF+5:0] ZManShifted; // output of the alignment shifter including sticky bit - logic [4*`NF+5:0] ZManPreShifted; // input to the alignment shifter + logic [4*`NF+5:0] ZManShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1) + logic [4*`NF+5:0] ZManPreShifted; // input to the alignment shifter U(NF+5.3NF+1) /////////////////////////////////////////////////////////////////////////////// // Calculate the product @@ -132,7 +132,7 @@ module fma1( // |1'b0| addnend | // the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...) - assign ZManPreShifted = {55'b0, {ZAssumed1E, ZFracE}, 106'b0}; + assign ZManPreShifted = {(`NF+3)'(0), {ZAssumed1E, ZFracE}, /*106*/(2*`NF+2)'(0)}; always_comb begin @@ -140,7 +140,7 @@ module fma1( // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - if ($signed(AlignCnt) <= $signed(-13'd56)) begin + if ($signed(AlignCnt) <= /*$signed(-13'd56)*/-(`NF+4)) begin KillProdE = 1; ZManShifted = ZManPreShifted;//{107'b0, {~ZAssumed1E, ZFrac}, 54'b0}; AddendStickyE = ~(XZeroE|YZeroE); @@ -149,7 +149,7 @@ module fma1( // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - end else if($signed(AlignCnt) <= $signed(13'd0)) begin + end else if($signed(AlignCnt) <= 0) begin KillProdE = 0; ZManShifted = ZManPreShifted << -AlignCnt; AddendStickyE = |(ZManShifted[51:0]); @@ -158,7 +158,7 @@ module fma1( // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - end else if ($signed(AlignCnt)<=$signed(13'd106)) begin + end else if ($signed(AlignCnt)<=(2*`NF+2)) begin KillProdE = 0; ZManShifted = ZManPreShifted >> AlignCnt; AddendStickyE = |(ZManShifted[51:0]); @@ -176,7 +176,7 @@ module fma1( end end - assign AlignedAddendE = ZManShifted[213:52]; + assign AlignedAddendE = ZManShifted[(4*`NF+5):`NF]; endmodule From b2f7952b3de891d9c4328a18b8d532c954a9d1a8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 19 Jul 2021 18:19:46 -0400 Subject: [PATCH 2/2] Added cache configuration to config files --- wally-pipelined/config/buildroot/wally-config.vh | 8 ++++++++ wally-pipelined/config/busybear/wally-config.vh | 8 ++++++++ wally-pipelined/config/coremark-64i/wally-config.vh | 11 +++++++++++ wally-pipelined/config/coremark/wally-config.vh | 8 ++++++++ wally-pipelined/config/coremark_bare/wally-config.vh | 8 ++++++++ wally-pipelined/config/rv32ic/wally-config.vh | 8 ++++++++ wally-pipelined/config/rv32icfd/wally-config.vh | 8 ++++++++ wally-pipelined/config/rv64BP/wally-config.vh | 8 ++++++++ wally-pipelined/config/rv64ic/wally-config.vh | 8 ++++++++ wally-pipelined/config/rv64icfd/wally-config.vh | 8 ++++++++ wally-pipelined/config/rv64imc/wally-config.vh | 8 ++++++++ 11 files changed, 91 insertions(+) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 3a834ab09..8bf0b381d 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -49,9 +49,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index d38228634..8ad4292b9 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -50,9 +50,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh index ae3100c6f..ade6f3cb5 100644 --- a/wally-pipelined/config/coremark-64i/wally-config.vh +++ b/wally-pipelined/config/coremark-64i/wally-config.vh @@ -50,6 +50,17 @@ // Bus Interface width `define AHBW 64 +// TLB configuration. Entries should be a power of 2 +`define ITLB_ENTRIES 32 +`define DTLB_ENTRIES 32 + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index e4e3376db..b8fc305c7 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -49,9 +49,17 @@ `define MEM_VIRTMEM 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Address space `define RESET_VECTOR 64'h00000000000100b0 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 45f04cffb..8d3fcfe75 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -50,9 +50,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 8b63c56a5..d6b3327cb 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -48,9 +48,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/rv32icfd/wally-config.vh b/wally-pipelined/config/rv32icfd/wally-config.vh index 28fc5a503..2b9f9dfd7 100644 --- a/wally-pipelined/config/rv32icfd/wally-config.vh +++ b/wally-pipelined/config/rv32icfd/wally-config.vh @@ -48,9 +48,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 01680b9d8..aa9b96a9c 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -50,9 +50,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Address space `define RESET_VECTOR 64'h0000000000000000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 3235c6233..aed12cb9f 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -49,9 +49,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index ac7f4ec61..f2d0816c5 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -49,9 +49,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index 925e98659..a51a951e1 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -48,9 +48,17 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +// TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 `define DTLB_ENTRIES 32 +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_REPLBITS 3 + // Address space `define RESET_VECTOR 64'h0000000080000000