mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
light cleanup for privileged tests
This commit is contained in:
parent
985c20c961
commit
9ff4025844
@ -1483,13 +1483,13 @@ string imperas32f[] = '{
|
|||||||
|
|
||||||
string wally64priv[] = '{
|
string wally64priv[] = '{
|
||||||
`WALLYTEST,
|
`WALLYTEST,
|
||||||
"rv64i_m/privilege/WALLY-MMU-SV39", "30A0",
|
"rv64i_m/privilege/WALLY-MMU-SV39", "40A0",
|
||||||
"rv64i_m/privilege/WALLY-MMU-SV48", "30A0",
|
"rv64i_m/privilege/WALLY-MMU-SV48", "40A0",
|
||||||
"rv64i_m/privilege/WALLY-PMP", "30A0",
|
"rv64i_m/privilege/WALLY-PMP", "40A0",
|
||||||
"rv64i_m/privilege/WALLY-PMA", "30A0",
|
"rv64i_m/privilege/WALLY-PMA", "40A0",
|
||||||
"rv64i_m/privilege/WALLY-minfo-01", "30A0",
|
"rv64i_m/privilege/WALLY-minfo-01", "40A0",
|
||||||
"rv64i_m/privilege/WALLY-CSR-permission-s-01", "40A0",
|
"rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0",
|
||||||
"rv64i_m/privilege/WALLY-CSR-permission-u-01", "40A0"
|
"rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0"
|
||||||
};
|
};
|
||||||
|
|
||||||
string wally64periph[] = '{
|
string wally64periph[] = '{
|
||||||
|
@ -63,9 +63,8 @@ copy:
|
|||||||
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
||||||
$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
|
$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
|
||||||
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
||||||
$(V) echo "Copying References without simulating for the following tests:"
|
$(V) echo "Copying References without simulating for the following tests: $(target_tests_nosim)"
|
||||||
$(V) echo $(target_tests_nosim)
|
$(V) for test in $(target_tests_nosim); do grep -o '^[^#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
|
||||||
$(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
|
|
||||||
|
|
||||||
compile: $(combined_elf)
|
compile: $(combined_elf)
|
||||||
run: $(target_log)
|
run: $(target_log)
|
||||||
|
@ -523,14 +523,13 @@ trap_return_pagetype_table:
|
|||||||
// Input parameters:
|
// Input parameters:
|
||||||
//
|
//
|
||||||
// x28:
|
// x28:
|
||||||
// Address input for the test taking place (think address to read/write, new address to return to, etc...)
|
// Address input for the test taking place (think: address to read/write, new address to return to, etc...)
|
||||||
//
|
//
|
||||||
// x29:
|
// x29:
|
||||||
// Value input for the test taking place (think value to write, any other extra info needed)
|
// Value input for the test taking place (think: value to write, any other extra info needed)
|
||||||
//
|
//
|
||||||
// x30:
|
// x30:
|
||||||
// Test type input that determines which kind of test will take place. Encoding for this input is in the table/case statements below
|
// Label for the location of the test that's about to take place
|
||||||
//
|
|
||||||
// ------------------------------------------------------------------------------------------------------------------------------------
|
// ------------------------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
.macro INIT_TEST_TABLE // *** Consider renaming this test. to what???
|
.macro INIT_TEST_TABLE // *** Consider renaming this test. to what???
|
||||||
@ -658,30 +657,15 @@ goto_u_mode:
|
|||||||
|
|
||||||
goto_baremetal:
|
goto_baremetal:
|
||||||
// Turn translation off
|
// Turn translation off
|
||||||
li x7, 0 // satp.MODE value for bare metal (0)
|
GOTO_BAREMETAL
|
||||||
slli x7, x7, 60
|
|
||||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field.
|
|
||||||
add x7, x7, x28
|
|
||||||
csrw satp, x7
|
|
||||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
|
||||||
j test_loop // go to next test case
|
j test_loop // go to next test case
|
||||||
|
|
||||||
goto_sv39:
|
goto_sv39:
|
||||||
li x7, 8 // satp.MODE value for Sv39 (8)
|
GOTO_SV39
|
||||||
slli x7, x7, 60
|
|
||||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field.
|
|
||||||
add x7, x7, x28
|
|
||||||
csrw satp, x7
|
|
||||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
|
||||||
j test_loop // go to next test case
|
j test_loop // go to next test case
|
||||||
|
|
||||||
goto_sv48:
|
goto_sv48:
|
||||||
li x7, 9 // satp.MODE value for Sv48
|
GOTO_SV48
|
||||||
slli x7, x7, 60
|
|
||||||
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field.
|
|
||||||
add x7, x7, x28
|
|
||||||
csrw satp, x7
|
|
||||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
|
||||||
j test_loop // go to next test case
|
j test_loop // go to next test case
|
||||||
|
|
||||||
write_mxr_sum:
|
write_mxr_sum:
|
||||||
@ -699,14 +683,16 @@ write_pmpcfg_0:
|
|||||||
// writes the value in x29 to the pmpcfg register specified in x28.
|
// writes the value in x29 to the pmpcfg register specified in x28.
|
||||||
// then writes the final value of pmpcfgX to the output.
|
// then writes the final value of pmpcfgX to the output.
|
||||||
li x7, 0x0
|
li x7, 0x0
|
||||||
bne x7, x28, write_pmpcfg_2
|
|
||||||
csrw pmpcfg0, x29
|
csrw pmpcfg0, x29
|
||||||
csrr x30, pmpcfg0
|
csrr x30, pmpcfg0
|
||||||
|
j write_pmpcfg_end
|
||||||
|
|
||||||
write_pmpcfg_2:
|
write_pmpcfg_2:
|
||||||
li x7, 0x2
|
li x7, 0x2
|
||||||
bne x7, x28, write_pmpcfg_end
|
|
||||||
csrw pmpcfg2, x29
|
csrw pmpcfg2, x29
|
||||||
csrr x30, pmpcfg2 // I would use csrrw but we need the value AFTER the csr has been written
|
csrr x30, pmpcfg2 // I would use csrrw but we need the value AFTER the csr has been written
|
||||||
|
j write_pmpcfg_end
|
||||||
|
|
||||||
write_pmpcfg_end:
|
write_pmpcfg_end:
|
||||||
sd x30, 0(x6)
|
sd x30, 0(x6)
|
||||||
addi x6, x6, 8
|
addi x6, x6, 8
|
||||||
@ -718,100 +704,100 @@ write_pmpaddr_0:
|
|||||||
// writes the value in x29 to the pmpaddr register specified in x28.
|
// writes the value in x29 to the pmpaddr register specified in x28.
|
||||||
// then writes the final value of pmpaddrX to the output.
|
// then writes the final value of pmpaddrX to the output.
|
||||||
li x7, 0x0
|
li x7, 0x0
|
||||||
bne x7, x28, write_pmpaddr_1
|
|
||||||
csrw pmpaddr0, x29
|
csrw pmpaddr0, x29
|
||||||
csrr x30, pmpaddr0
|
csrr x30, pmpaddr0
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_1:
|
write_pmpaddr_1:
|
||||||
li x7, 0x1
|
li x7, 0x1
|
||||||
bne x7, x28, write_pmpaddr_2
|
|
||||||
csrw pmpaddr1, x29
|
csrw pmpaddr1, x29
|
||||||
csrr x30, pmpaddr1
|
csrr x30, pmpaddr1
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_2:
|
write_pmpaddr_2:
|
||||||
li x7, 0x2
|
li x7, 0x2
|
||||||
bne x7, x28, write_pmpaddr_3
|
|
||||||
csrw pmpaddr2, x29
|
csrw pmpaddr2, x29
|
||||||
csrr x30, pmpaddr2
|
csrr x30, pmpaddr2
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_3:
|
write_pmpaddr_3:
|
||||||
li x7, 0x3
|
li x7, 0x3
|
||||||
bne x7, x28, write_pmpaddr_4
|
|
||||||
csrw pmpaddr3, x29
|
csrw pmpaddr3, x29
|
||||||
csrr x30, pmpaddr3
|
csrr x30, pmpaddr3
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_4:
|
write_pmpaddr_4:
|
||||||
li x7, 0x4
|
li x7, 0x4
|
||||||
bne x7, x28, write_pmpaddr_5
|
|
||||||
csrw pmpaddr4, x29
|
csrw pmpaddr4, x29
|
||||||
csrr x30, pmpaddr4
|
csrr x30, pmpaddr4
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_5:
|
write_pmpaddr_5:
|
||||||
li x7, 0x5
|
li x7, 0x5
|
||||||
bne x7, x28, write_pmpaddr_6
|
|
||||||
csrw pmpaddr5, x29
|
csrw pmpaddr5, x29
|
||||||
csrr x30, pmpaddr5
|
csrr x30, pmpaddr5
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_6:
|
write_pmpaddr_6:
|
||||||
li x7, 0x6
|
li x7, 0x6
|
||||||
bne x7, x28, write_pmpaddr_7
|
|
||||||
csrw pmpaddr6, x29
|
csrw pmpaddr6, x29
|
||||||
csrr x30, pmpaddr6
|
csrr x30, pmpaddr6
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_7:
|
write_pmpaddr_7:
|
||||||
li x7, 0x7
|
li x7, 0x7
|
||||||
bne x7, x28, write_pmpaddr_8
|
|
||||||
csrw pmpaddr7, x29
|
csrw pmpaddr7, x29
|
||||||
csrr x30, pmpaddr7
|
csrr x30, pmpaddr7
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_8:
|
write_pmpaddr_8:
|
||||||
li x7, 0x8
|
li x7, 0x8
|
||||||
bne x7, x28, write_pmpaddr_9
|
|
||||||
csrw pmpaddr8, x29
|
csrw pmpaddr8, x29
|
||||||
csrr x30, pmpaddr8
|
csrr x30, pmpaddr8
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_9:
|
write_pmpaddr_9:
|
||||||
li x7, 0x9
|
li x7, 0x9
|
||||||
bne x7, x28, write_pmpaddr_10
|
|
||||||
csrw pmpaddr9, x29
|
csrw pmpaddr9, x29
|
||||||
csrr x30, pmpaddr9
|
csrr x30, pmpaddr9
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_10:
|
write_pmpaddr_10:
|
||||||
li x7, 0xA
|
li x7, 0xA
|
||||||
bne x7, x28, write_pmpaddr_11
|
|
||||||
csrw pmpaddr10, x29
|
csrw pmpaddr10, x29
|
||||||
csrr x30, pmpaddr10
|
csrr x30, pmpaddr10
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_11:
|
write_pmpaddr_11:
|
||||||
li x7, 0xB
|
li x7, 0xB
|
||||||
bne x7, x28, write_pmpaddr_12
|
|
||||||
csrw pmpaddr11, x29
|
csrw pmpaddr11, x29
|
||||||
csrr x30, pmpaddr11
|
csrr x30, pmpaddr11
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_12:
|
write_pmpaddr_12:
|
||||||
li x7, 0xC
|
li x7, 0xC
|
||||||
bne x7, x28, write_pmpaddr_13
|
|
||||||
csrw pmpaddr12, x29
|
csrw pmpaddr12, x29
|
||||||
csrr x30, pmpaddr12
|
csrr x30, pmpaddr12
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_13:
|
write_pmpaddr_13:
|
||||||
li x7, 0xD
|
li x7, 0xD
|
||||||
bne x7, x28, write_pmpaddr_14
|
|
||||||
csrw pmpaddr13, x29
|
csrw pmpaddr13, x29
|
||||||
csrr x30, pmpaddr13
|
csrr x30, pmpaddr13
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_14:
|
write_pmpaddr_14:
|
||||||
li x7, 0xE
|
li x7, 0xE
|
||||||
bne x7, x28, write_pmpaddr_15
|
|
||||||
csrw pmpaddr14, x29
|
csrw pmpaddr14, x29
|
||||||
csrr x30, pmpaddr14
|
csrr x30, pmpaddr14
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_15:
|
write_pmpaddr_15:
|
||||||
li x7, 0xF
|
li x7, 0xF
|
||||||
bne x7, x28, write_pmpaddr_end
|
|
||||||
csrw pmpaddr15, x29
|
csrw pmpaddr15, x29
|
||||||
csrr x30, pmpaddr15
|
csrr x30, pmpaddr15
|
||||||
j write_pmpaddr_end
|
j write_pmpaddr_end
|
||||||
|
|
||||||
write_pmpaddr_end:
|
write_pmpaddr_end:
|
||||||
sd x30, 0(x6)
|
sd x30, 0(x6)
|
||||||
addi x6, x6, 8
|
addi x6, x6, 8
|
||||||
|
Loading…
Reference in New Issue
Block a user