From 9fdb1d3cc9cef43d74077dfbcf695ec74bf0f922 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 24 Sep 2021 11:30:52 -0500
Subject: [PATCH] setup so the sdc does not need to load a model in the imperas
 test bench.

---
 wally-pipelined/src/sdc/tb/sd_top_tb.sv     | 2 ++
 wally-pipelined/testbench/common/sdModel.sv | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/sdc/tb/sd_top_tb.sv b/wally-pipelined/src/sdc/tb/sd_top_tb.sv
index 11bb2cadb..21ce7fd5b 100644
--- a/wally-pipelined/src/sdc/tb/sd_top_tb.sv
+++ b/wally-pipelined/src/sdc/tb/sd_top_tb.sv
@@ -88,6 +88,8 @@ module sd_top_tb();
     end
   
 
+  initial $readmemh("ramdisk2.hex", sdcard.FLASHmem);
+  
   initial begin
 
     a_RST          = 1'b0;
diff --git a/wally-pipelined/testbench/common/sdModel.sv b/wally-pipelined/testbench/common/sdModel.sv
index 29f2336d0..52795dd05 100644
--- a/wally-pipelined/testbench/common/sdModel.sv
+++ b/wally-pipelined/testbench/common/sdModel.sv
@@ -24,7 +24,7 @@ module    sdModel
    inout tri1       cmd,
    inout tri1 [3:0] dat
    );
-   parameter SD_FILE = "ramdisk2.hex";
+   //parameter SD_FILE = "ramdisk2.hex";
    
    reg 	     oeCmd;
    reg 	     oeDat;
@@ -142,7 +142,7 @@ module    sdModel
    reg 	     q_start_bit;
    
    //Card initialization DAT contents
-   initial $readmemh(SD_FILE, FLASHmem);
+   //initial $readmemh(SD_FILE, FLASHmem);
 
    initial begin
       wide_data[0] <= 00;