diff --git a/README.md b/README.md
index 9cb56de0d..b73aecdb8 100644
--- a/README.md
+++ b/README.md
@@ -1,12 +1,15 @@
 # core-v-wally
-Configurable RISC-V Processor
 
-Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.
+Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO).   Wally is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.  Configurations range from a minimal RV32E core to a fully featured RV64GC application processor.
 
 ![Wally block diagram](wallyriscvTopAll.png)
 
 Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
 
+# Verification
+
+Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplan.md) for details.
+
 # New User Setup
 
 New users may wish to do the following setup to access the server via a GUI and use a text editor.
diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
index 92f64cbdc..f4d465012 100644
--- a/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -57,43 +57,43 @@ module fdivsqrt(
 
   logic [`DIVb+3:0]           WS, WC;                       // Partial remainder components
   logic [`DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
-  logic [`DIVb-1:0]           DPreproc, D;                  // Iterator Divisor
+  logic [`DIVb+3:0]           D;                            // Iterator Divisor
   logic [`DIVb:0]             FirstU, FirstUM;              // Intermediate result values
   logic [`DIVb+1:0]           FirstC;                       // Step tracker
   logic                       Firstun;                      // Quotient selection
   logic                       WZeroE;                       // Early termination flag
+  logic [`DURLEN-1:0]         cycles;                       // FSM cycles
   logic                       SpecialCaseM;                 // Divide by zero, square root of negative, etc.
   logic                       DivStartE;                    // Enable signal for flops during stall
                                                             
   // Integer div/rem signals                                
   logic                       BZeroM;                       // Denominator is zero
   logic                       IntDivM;                      // Integer operation
-  logic [`DIVBLEN:0]          nE, nM, mM;                   // Shift amounts
+  logic [`DIVBLEN:0]          nM, mM;                       // Shift amounts
   logic                       NegQuotM, ALTBM, AsM, W64M;   // Special handling for postprocessor
   logic [`XLEN-1:0]           AM;                           // Original Numerator for postprocessor
   logic                       ISpecialCaseE;                // Integer div/remainder special cases
 
-  fdivsqrtpreproc fdivsqrtpreproc(                        // Preprocessor
-    .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), 
-    .Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E, 
-    .QeM, .X, .DPreproc, 
+  fdivsqrtpreproc fdivsqrtpreproc(                          // Preprocessor
+    .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
+    .FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .cycles,
     // Int-specific 
     .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
-    .nE, .BZeroM, .nM, .mM, .AM, 
+    .BZeroM, .nM, .mM, .AM, 
     .IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
 
-  fdivsqrtfsm fdivsqrtfsm(                                // FSM
-    .clk, .reset, .FmtE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
+  fdivsqrtfsm fdivsqrtfsm(                                  // FSM
+    .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
     .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, 
-    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, 
+    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .cycles,
     // Int-specific 
-    .IDivStartE, .ISpecialCaseE, .nE, .IntDivE);
+    .IDivStartE, .ISpecialCaseE, .IntDivE);
 
-  fdivsqrtiter fdivsqrtiter(                              // CSA Iterator
-    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc, 
-    .D, .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
+  fdivsqrtiter fdivsqrtiter(                                // CSA Iterator
+    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
+    .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
 
-  fdivsqrtpostproc fdivsqrtpostproc(                      // Postprocessor
+  fdivsqrtpostproc fdivsqrtpostproc(                        // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
     .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
     .QmM, .WZeroE, .DivStickyM, 
diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
new file mode 100644
index 000000000..f1ad32cd8
--- /dev/null
+++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
@@ -0,0 +1,76 @@
+///////////////////////////////////////////
+// fdivsqrt.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
+// Modified: 18 April 2022
+//
+// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtcycles(
+  input  logic [`FMTBITS-1:0] FmtE,
+  input  logic                SqrtE,
+  input  logic                IntDivE,
+  input  logic [`DIVBLEN:0]   nE,
+  output logic [`DURLEN-1:0]  cycles
+);
+  logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
+  // DIVN = `NF+3
+  // NS = NF + 1
+  // N = NS or NS+2 for div/sqrt.
+
+  /* verilator lint_off WIDTH */
+  if (`FPSIZES == 1)
+    assign Nf = `NF;
+  else if (`FPSIZES == 2)
+    always_comb
+      case (FmtE)
+        1'b0: Nf = `NF1;
+        1'b1: Nf = `NF;
+      endcase
+  else if (`FPSIZES == 3)
+    always_comb
+      case (FmtE)
+        `FMT:  Nf = `NF;
+        `FMT1: Nf = `NF1;
+        `FMT2: Nf = `NF2; 
+      endcase
+  else if (`FPSIZES == 4)  
+    always_comb
+      case(FmtE)
+        `S_FMT: Nf = `S_NF;
+        `D_FMT: Nf = `D_NF;
+        `H_FMT: Nf = `H_NF;
+        `Q_FMT: Nf = `Q_NF;
+      endcase 
+
+  always_comb begin 
+    if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
+    else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
+    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+  end 
+  /* verilator lint_on WIDTH */
+
+endmodule
\ No newline at end of file
diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 0793346bf..5332087ad 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -29,32 +29,27 @@
 `include "wally-config.vh"
 
 module fdivsqrtfsm(
-  input  logic                clk, 
-  input  logic                reset, 
-  input  logic [`FMTBITS-1:0] FmtE,
-  input  logic                XInfE, YInfE, 
-  input  logic                XZeroE, YZeroE, 
-  input  logic                XNaNE, YNaNE, 
-  input  logic                FDivStartE, IDivStartE,
-  input  logic                XsE,
-  input  logic                SqrtE,
-  input  logic                StallM,
-  input  logic                FlushE,
-  input  logic                WZeroE,
-  input  logic                IntDivE,
-  input  logic [`DIVBLEN:0]   nE,
-  input  logic                ISpecialCaseE,
-  output logic                IFDivStartE,
-  output logic                FDivBusyE, FDivDoneE,
-  output logic                SpecialCaseM
+  input  logic               clk, reset, 
+  input  logic               XInfE, YInfE, 
+  input  logic               XZeroE, YZeroE, 
+  input  logic               XNaNE, YNaNE, 
+  input  logic               FDivStartE, IDivStartE,
+  input  logic               XsE, WZeroE,
+  input  logic               SqrtE,
+  input  logic               StallM, FlushE,
+  input  logic               IntDivE,
+  input  logic               ISpecialCaseE,
+  input  logic [`DURLEN-1:0] cycles,
+  output logic               IFDivStartE,
+  output logic               FDivBusyE, FDivDoneE,
+  output logic               SpecialCaseM
 );
   
   typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
   statetype state;
 
-  logic [`DURLEN-1:0] step;
-  logic [`DURLEN-1:0] cycles;
   logic SpecialCaseE, FSpecialCaseE;
+  logic [`DURLEN-1:0] step;
 
   // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
   assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
@@ -67,47 +62,6 @@ module fdivsqrtfsm(
   else              assign SpecialCaseE = FSpecialCaseE;
   flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
 
-// DIVN = `NF+3
-// NS = NF + 1
-// N = NS or NS+2 for div/sqrt.  
-
-// *** CT 4/13/23 move cycles calculation back to preprocesor
-/* verilator lint_off WIDTH */
-  logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
-  if (`FPSIZES == 1)
-    assign Nf = `NF;
-  else if (`FPSIZES == 2)
-    always_comb
-      case (FmtE)
-        1'b0: Nf = `NF1;
-        1'b1: Nf = `NF;
-      endcase
-  else if (`FPSIZES == 3)
-    always_comb
-      case (FmtE)
-        `FMT: Nf = `NF;
-        `FMT1: Nf = `NF1;
-        `FMT2: Nf = `NF2; 
-      endcase
-  else if (`FPSIZES == 4)  
-    always_comb
-      case(FmtE)
-        `S_FMT: Nf = `S_NF;
-        `D_FMT: Nf = `D_NF;
-        `H_FMT: Nf = `H_NF;
-        `Q_FMT: Nf = `Q_NF;
-      endcase 
-
-
-  always_comb begin 
-    if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
-    else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
-    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
-    else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
-  end 
-
-  /* verilator lint_on WIDTH */
-
   always_ff @(posedge clk) begin
       if (reset | FlushE) begin
           state <= #1 IDLE; 
diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
index ec15423e4..aeb4bcc4d 100644
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -33,9 +33,7 @@ module fdivsqrtiter(
   input  logic             IFDivStartE, 
   input  logic             FDivBusyE, 
   input  logic             SqrtE,
-  input  logic [`DIVb+3:0] X,
-  input  logic [`DIVb-1:0] DPreproc,
-  output logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0] X, D,
   output logic [`DIVb:0]   FirstU, FirstUM,
   output logic [`DIVb+1:0] FirstC,
   output logic             Firstun,
@@ -95,16 +93,11 @@ module fdivsqrtiter(
   mux2   #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
   flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
 
-   // Divisior register
-  flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
-
   // Divisor Selections
-  //  - choose the negitive version of what's being selected
-  //  - D is a 0.b mantissa
-  assign DBar    = {3'b111, 1'b0, ~D};
+  assign DBar    = ~D;        // for -D
   if(`RADIX == 4) begin : d2
-    assign DBar2 = {2'b11, 1'b0, ~D, 1'b1};
-    assign D2    = {2'b0, 1'b1, D, 1'b0};
+    assign D2    = D << 1;    // for 2D,  only used in R4
+    assign DBar2 = ~D2;       // for -2D, only used in R4
   end
 
   // k=DIVCOPIES of the recurrence logic
diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index b8575f7fe..1009cd227 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -32,7 +32,7 @@ module fdivsqrtpostproc(
   input  logic              clk, reset,
   input  logic              StallM,
   input  logic [`DIVb+3:0]  WS, WC,
-  input  logic [`DIVb-1:0]  D, 
+  input  logic [`DIVb+3:0]  D, 
   input  logic [`DIVb:0]    FirstU, FirstUM, 
   input  logic [`DIVb+1:0]  FirstC,
   input  logic              SqrtE,
@@ -46,7 +46,7 @@ module fdivsqrtpostproc(
   output logic [`XLEN-1:0]  FIntDivResultM
 );
   
-  logic [`DIVb+3:0]         W, Sum, DM;
+  logic [`DIVb+3:0]         W, Sum;
   logic [`DIVb:0]           PreQmM;
   logic                     NegStickyM;
   logic                     weq0E, WZeroM;
@@ -67,7 +67,7 @@ module fdivsqrtpostproc(
 
     assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
     assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
-    assign FZeroDivE =  {3'b001,D,1'b0};                                    // F for divide
+    assign FZeroDivE =  D << 1;                                    // F for divide
     mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
     csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
@@ -102,11 +102,10 @@ module fdivsqrtpostproc(
     logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
 
     assign W = $signed(Sum) >>> `LOGR;
-    assign DM = {4'b0001, D};
     assign UnsignedQuotM = {3'b000, PreQmM};
 
     // Integer remainder: sticky and sign correction muxes
-    mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
+    mux2 #(`DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
     mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
     mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index cf8a055ef..43a5e42b2 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -33,29 +33,29 @@ module fdivsqrtpreproc (
   input  logic                IFDivStartE, 
   input  logic [`NF:0]        Xm, Ym,
   input  logic [`NE-1:0]      Xe, Ye,
-  input  logic [`FMTBITS-1:0] Fmt,
-  input  logic                Sqrt,
+  input  logic [`FMTBITS-1:0] FmtE,
+  input  logic                SqrtE,
   input  logic                XZeroE,
   input  logic [2:0]          Funct3E,
   output logic [`NE+1:0]      QeM,
-  output logic [`DIVb+3:0]    X,
-  output logic [`DIVb-1:0]    DPreproc,
+  output logic [`DIVb+3:0]    X, D,
   // Int-specific
   input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   input  logic                IntDivE, W64E,
   output logic                ISpecialCaseE,
-  output logic [`DIVBLEN:0]   nE, nM, mM,
+  output logic [`DURLEN-1:0]  cycles,
+  output logic [`DIVBLEN:0]   nM, mM,
   output logic                NegQuotM, ALTBM, IntDivM, W64M,
   output logic                AsM, BZeroM,
   output logic [`XLEN-1:0]    AM
 );
 
-  logic [`DIVb-1:0]           XPreproc;
+  logic [`DIVb-1:0]           XPreproc, DPreproc;
   logic [`DIVb:0]             PreSqrtX;
   logic [`DIVb+3:0]           DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
   logic [`NE+1:0]             QeE;                                 // Quotient Exponent (FP only)
   logic [`DIVb-1:0]           IFX, IFD;                            // Correctly-sized inputs for iterator, selected from int or fp input
-  logic [`DIVBLEN:0]          mE, ell;                             // Leading zeros of inputs
+  logic [`DIVBLEN:0]          mE, nE, ell;                             // Leading zeros of inputs
   logic                       NumerZeroE;                          // Numerator is zero (X or A)
   logic                       AZeroE, BZeroE;                      // A or B is Zero for integer division
   logic                       signedDiv;                           // signed division
@@ -111,7 +111,9 @@ module fdivsqrtpreproc (
   // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
   mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
   assign DivX = {3'b000, ~NumerZeroE, XPreproc};
-  // *** CT 4/13/23 Create D output here with leading 1 appended as well, use in the other modules
+
+   // Divisior register
+  flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D);
 
   // ***CT: factor out fdivsqrtcycles
   if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
@@ -168,10 +170,13 @@ module fdivsqrtpreproc (
   // Sqrt is initialized on step one as R(X-1), so depends on Radix
   if (`RADIX == 2)  assign SqrtX = {3'b111, PreSqrtX};
   else              assign SqrtX = {2'b11, PreSqrtX, 1'b0};
-  mux2 #(`DIVb+4) prexmux(DivX, SqrtX, Sqrt, PreShiftX);
+  mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
  
   // Floating-point exponent
-  fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
+  fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
   flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
+
+  // Number of FSM cycles (to FSM)
+  fdivsqrtcycles cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .cycles);
 endmodule
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
index 53c1711cb..be62f8aa6 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@@ -30,8 +30,7 @@
 
 /* verilator lint_off UNOPTFLAT */
 module fdivsqrtstage2 (
-  input  logic [`DIVb-1:0] D,
-  input  logic [`DIVb+3:0] DBar, 
+  input  logic [`DIVb+3:0] D, DBar, 
   input  logic [`DIVb:0]   U, UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
@@ -66,7 +65,7 @@ module fdivsqrtstage2 (
   always_comb
     if      (up) Dsel = DBar;
     else if (uz) Dsel = '0;
-    else         Dsel = {4'b0001, D}; // un
+    else         Dsel = D; // un
 
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
index f2ff3734b..9464e6a88 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -29,8 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtstage4 (
-  input  logic [`DIVb-1:0] D,
-  input  logic [`DIVb+3:0] DBar, D2, DBar2,
+  input  logic [`DIVb+3:0] D, DBar, D2, DBar2,
   input  logic [`DIVb:0]   U,UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
@@ -75,7 +74,7 @@ module fdivsqrtstage4 (
       4'b1000: Dsel = DBar2;
       4'b0100: Dsel = DBar;
       4'b0000: Dsel = '0;
-      4'b0010: Dsel = {3'b0, 1'b1, D};
+      4'b0010: Dsel = D;
       4'b0001: Dsel = D2;
       default: Dsel = 'x;
     endcase
diff --git a/testbench/tests.vh b/testbench/tests.vh
index e2d4e5ad1..a450b057d 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -59,6 +59,10 @@ string tvpaths[] = '{
     "pmpcfg1",
     "pmpcfg2",
     "tlbKP",
+    "tlbMP",
+    "tlbM3",
+    "tlbASID",
+    "tlbGLB",
     "ifuCamlineWrite"
   };
 
diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S
new file mode 100644
index 000000000..bf71c0491
--- /dev/null
+++ b/tests/coverage/tlbASID.S
@@ -0,0 +1,133 @@
+///////////////////////////////////////////
+// tlbASID.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080080 // try making asid = 0. 
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0xC0000000
+
+    li t2, 0             # i = 0
+    li t5, 0            # j = 0 // now use as a counter for new asid loop 
+    li t3, 32     # Max amount of Loops = 32
+
+loop: bge t2, t3, nASID   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t4, 0x1000
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+nASID: bne t5, zero, finished
+    li a0, 3   // go
+    ecall
+    li t5, 0x9000100000080080 // try making asid = 1 
+    csrw satp, t5
+    li a0, 1   
+    ecall
+    li t2, 0
+    li t0, 0xC0000000
+    li t5, 1 // make this not zero. 
+    j loop
+
+
+finished:
+    j done
+
+.data
+.align 19
+# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
+pagetable: 
+    .8byte 0x200204C1
+    
+.align 12 // level 2 page table, contains direction to a gigapageg
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
+    .8byte 0x200208C1 // pointer to next page table entry at 8008 2000
+
+.align 12 // level 1 page table, points to level 0 page table
+    .8byte 0x20020CC1
+
+.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
+    .8byte 0x200000CF // access xC000 0000
+    .8byte 0x200004CF // access xC000 1000
+    .8byte 0x200008CF // access xC000 2000
+    .8byte 0x20000CCF // access xC000 3000
+
+    .8byte 0x200010CF // access xC000 4000
+    .8byte 0x200014CF
+    .8byte 0x200018CF
+    .8byte 0x20001CCF
+
+    .8byte 0x200020CF // access xC000 8000
+    .8byte 0x200024CF
+    .8byte 0x200028CF
+    .8byte 0x20002CCF
+
+    .8byte 0x200030CF // access xC000 C000
+    .8byte 0x200034CF
+    .8byte 0x200038CF
+    .8byte 0x20003CCF
+
+    .8byte 0x200040CF // access xC001 0000
+    .8byte 0x200044CF
+    .8byte 0x200048CF
+    .8byte 0x20004CCF
+
+    .8byte 0x200050CF // access xC001 4000
+    .8byte 0x200054CF
+    .8byte 0x200058CF
+    .8byte 0x20005CCF
+
+    .8byte 0x200060CF // access xC001 8000
+    .8byte 0x200064CF
+    .8byte 0x200068CF
+    .8byte 0x20006CCF
+
+    .8byte 0x200070CF // access xC001 C000
+    .8byte 0x200074CF
+    .8byte 0x200078CF
+    .8byte 0x20007CCF
+
+    .8byte 0x200080CF // access xC002 0000
+    .8byte 0x200084CF
+    .8byte 0x200088CF
+    .8byte 0x20008CCF
+
+    
\ No newline at end of file
diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S
new file mode 100644
index 000000000..77e3a31c1
--- /dev/null
+++ b/tests/coverage/tlbGLB.S
@@ -0,0 +1,134 @@
+///////////////////////////////////////////
+// tlbGLB.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: coverage for the global check. 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080080 // try making asid = 0. 
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0xC0000000
+
+    li t2, 0             # i = 0
+    li t5, 0            # j = 0 // now use as a counter for new asid loop 
+    li t3, 32     # Max amount of Loops = 32
+
+loop: bge t2, t3, nASID   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t4, 0x1000
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+nASID: bne t5, zero, finished
+    li a0, 3   // go
+    ecall
+    li t5, 0x9000100000080080 // try making asid = 1 
+    csrw satp, t5
+    li a0, 1   
+    ecall
+    li t2, 0
+    li t0, 0xC0000000
+    li t5, 1 // make this not zero. 
+    j loop
+
+
+finished:
+    j done
+
+.data
+.align 19
+# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
+pagetable: 
+    .8byte 0x200204C1
+    
+.align 12 // level 2 page table, contains direction to a gigapageg
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
+    .8byte 0x200208C1 // pointer to next page table entry at 8008 2000
+
+.align 12 // level 1 page table, points to level 0 page table
+    .8byte 0x20020CE1
+
+.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
+    .8byte 0x200000CF // access xC000 0000
+    .8byte 0x200004CF // access xC000 1000
+    .8byte 0x200008CF // access xC000 2000
+    .8byte 0x20000CCF // access xC000 3000
+
+    .8byte 0x200010EF // access xC000 4000
+    .8byte 0x200014EF
+    .8byte 0x200018EF
+    .8byte 0x20001CEF
+
+    .8byte 0x200020EF // access xC000 8000
+    .8byte 0x200024EF
+    .8byte 0x200028EF
+    .8byte 0x20002CEF
+
+    .8byte 0x200030EF // access xC000 C000
+    .8byte 0x200034EF
+    .8byte 0x200038EF
+    .8byte 0x20003CEF
+
+    .8byte 0x200040EF // access xC001 0000
+    .8byte 0x200044EF
+    .8byte 0x200048EF
+    .8byte 0x20004CEF
+
+    .8byte 0x200050EF // access xC001 4000
+    .8byte 0x200054EF
+    .8byte 0x200058EF
+    .8byte 0x20005CEF
+
+    .8byte 0x200060EF // access xC001 8000
+    .8byte 0x200064EF
+    .8byte 0x200068EF
+    .8byte 0x20006CEF
+
+    .8byte 0x200070EF // access xC001 C000
+    .8byte 0x200074eF
+    .8byte 0x200078EF
+    .8byte 0x20007CEF
+
+    .8byte 0x200080EF // access xC002 0000
+    .8byte 0x200084EF
+    .8byte 0x200088EF
+    .8byte 0x20008CEF
+
+    
\ No newline at end of file
diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S
new file mode 100644
index 000000000..ececa1f34
--- /dev/null
+++ b/tests/coverage/tlbM3.S
@@ -0,0 +1,155 @@
+///////////////////////////////////////////
+// tlbKP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0x1000
+
+    li t2, 0             # i = 0
+    li t3, 64     # Max amount of Loops = 32
+    li t4, 0x1000
+
+loop: bge t2, t3, interim  # exit loop if i >= loops
+    lw t1, 0(t0)
+    # sfence.vma x0, x0
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+interim:
+    li t0, 0xFFFFFFFF000
+    li t2, 0             # i = 0
+     
+
+loop2:bge t2, t3, finished  # exit loop if i >= loops
+    lw t1, 0(t0)
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop2
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
+
+.align 12
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    
+
+.align 12
+    .8byte 0x0000000020004CC1
+    //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
+
+.align 12
+    #80000000
+    .8byte 0x200000CF
+    .8byte 0x200004CF
+    .8byte 0x200008CF
+    .8byte 0x20000CCF
+
+    .8byte 0x200010CF
+    .8byte 0x200014CF
+    .8byte 0x200018CF
+    .8byte 0x20001CCF
+
+    .8byte 0x200020CF
+    .8byte 0x200024CF
+    .8byte 0x200028CF
+    .8byte 0x20002CCF
+
+    .8byte 0x200030CF
+    .8byte 0x200034CF
+    .8byte 0x200038CF
+    .8byte 0x20003CCF
+
+    .8byte 0x200040CF
+    .8byte 0x200044CF
+    .8byte 0x200048CF
+    .8byte 0x20004CCF
+
+    .8byte 0x200050CF
+    .8byte 0x200054CF
+    .8byte 0x200058CF
+    .8byte 0x20005CCF
+
+    .8byte 0x200060CF
+    .8byte 0x200064CF
+    .8byte 0x200068CF
+    .8byte 0x20006CCF
+
+    .8byte 0x200070CF
+    .8byte 0x200074CF
+    .8byte 0x200078CF
+    .8byte 0x20007CCF
+    
+    .8byte 0x200080CF
+    .8byte 0x200084CF
+    .8byte 0x200088CF
+    .8byte 0x20008CCF
+
+    .8byte 0x200090CF
+    .8byte 0x200094CF
+    .8byte 0x200098CF
+    .8byte 0x20009CCF
+
+    .8byte 0x2000A0CF
+    .8byte 0x2000A4CF
+    .8byte 0x2000A8CF
+    .8byte 0x2000ACCF
+
+    .8byte 0x2000B0CF
+    .8byte 0x2000B4CF
+    .8byte 0x2000B8CF
+    .8byte 0x2000BCCF
+
+    .8byte 0x2000C0CF
+    .8byte 0x2000C4CF
+    .8byte 0x2000C8CF
+    .8byte 0x2000CCCF
+
+    .8byte 0x2000D0CF
+    .8byte 0x2000D4CF
diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S
new file mode 100644
index 000000000..6981d1f36
--- /dev/null
+++ b/tests/coverage/tlbMP.S
@@ -0,0 +1,163 @@
+///////////////////////////////////////////
+// tlbMP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+    li t5, 0 
+    li t0, 0x84000000 // go to first megapage
+    li t4, 0x1000 // put this outside the loop.
+    li t2, 0      # i = 0
+    li t3, 32     # Max amount of Loops = 16
+
+loop: bge t2, t3, lKP   # exit loop if i >= loops
+    lw t1, 0(t0)
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+lKP: bne t5, zero, finished
+    li t0, 0x80000000 
+    slli t4, t4, 9
+    addi t5, t5, 1
+    li t2, 0
+    j loop
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1
+
+.align 12
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    
+
+.align 12 // megapages starting at 8000 0000 going to 8480 0000  (32*2 MiB beyond that)
+
+    .8byte 0x200000CF // access 8000,0000
+    .8byte 0x200800CF // access 8020,0000 
+    .8byte 0x201000CF // acesss 8040,0000
+    .8byte 0x201800CF // acesss 8060,0000
+
+    .8byte 0x202000CF // access 8080,0000
+    .8byte 0x202800CF // access 80A0,0000
+    .8byte 0x203000CF // access 80C0,0000
+    .8byte 0x203800CF // access 80E0,0000
+
+    .8byte 0x204000CF // access 8100,0000
+    .8byte 0x204800CF 
+    .8byte 0x205000CF 
+    .8byte 0x205800CF 
+
+    .8byte 0x206000CF // access 8180,0000
+    .8byte 0x206800CF 
+    .8byte 0x207000CF 
+    .8byte 0x207800CF 
+
+    .8byte 0x208000CF // access 8200,0000
+    .8byte 0x208800CF 
+    .8byte 0x209000CF 
+    .8byte 0x209800CF 
+
+    .8byte 0x20A000CF // access 8280,0000
+    .8byte 0x20A800CF 
+    .8byte 0x20B000CF 
+    .8byte 0x20B800CF 
+
+    .8byte 0x20C000CF // access 8300,0000
+    .8byte 0x20C800CF 
+    .8byte 0x20D000CF 
+    .8byte 0x20D800CF
+
+    .8byte 0x20E000CF // access 8380,0000
+    .8byte 0x20E800CF 
+    .8byte 0x20F000CF 
+    .8byte 0x20F800CF
+
+    .8byte 0x20004CC1
+     // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
+                      // point to ... 
+
+.align 12 // should start at 84000000 
+    .8byte 0x210000CF
+    .8byte 0x210004CF
+    .8byte 0x210008CF
+    .8byte 0x21000CCF
+
+    .8byte 0x210010CF
+    .8byte 0x210014CF
+    .8byte 0x210018CF
+    .8byte 0x21001CCF
+
+    .8byte 0x210020CF
+    .8byte 0x210024CF
+    .8byte 0x210028CF
+    .8byte 0x21002CCF
+
+    .8byte 0x210030CF
+    .8byte 0x210034CF
+    .8byte 0x210038CF
+    .8byte 0x21003CCF
+
+    .8byte 0x210040CF
+    .8byte 0x210044CF
+    .8byte 0x210048CF
+    .8byte 0x21004CCF
+
+    .8byte 0x210050CF
+    .8byte 0x210054CF
+    .8byte 0x210058CF
+    .8byte 0x21005CCF
+
+    .8byte 0x210060CF
+    .8byte 0x210064CF
+    .8byte 0x210068CF
+    .8byte 0x21006CCF
+
+    .8byte 0x210070CF
+    .8byte 0x210074CF
+    .8byte 0x210078CF
+    .8byte 0x21007CCF
+