Merge pull request #545 from davidharrishmc/dev

Coverage Improvements and Verilator progress

.gitignore

@@ -182,3 +182,5 @@ benchmarks/embench/run*
 sim/cfi.log
 sim/cfi/*
 sim/branch/*
+sim/obj_dir
+examples/verilog/fulladder/obj_dir

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit eb0a3892215ad2384702db02da1551a59701ec67
+Subproject commit c955abf757df98cf38809e40a62d2a6b448ea507

bin/wally-tool-chain-install.sh

@@ -166,7 +166,7 @@ sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 
 # riscof
 sudo pip3 install -U testresources riscv_config
-pip3 install git+https://github.com/riscv/riscof.git
+sudo pip3 install git+https://github.com/riscv/riscof.git
 
 # Download OSU Skywater 130 cell library
 sudo mkdir -p $RISCV/cad/lib

examples/verilog/fulladder/fulladder.sv

@@ -3,6 +3,7 @@ module testbench();
   logic        a, b, c, s, cout, sexpected, coutexpected;
   logic [31:0] vectornum, errors;
   logic [4:0]  testvectors[10000:0];
+  integer cycle;
 
   // instantiate device under test
   fulladder dut(a, b, c, s, cout);
@@ -11,12 +12,15 @@ module testbench();
   always 
     begin
       clk = 1; #5; clk = 0; #5;
+      cycle = cycle + 1;
+      $display("cycle: %x vectornum %x testvectors[vectornum]: %b", cycle, vectornum, testvectors[vectornum]);
     end
 
   // at start of test, load vectors and pulse reset
   initial
     begin
       $readmemb("fulladder.tv", testvectors);
+      cycle = 0;
       vectornum = 0; errors = 0;
       reset = 1; #22; reset = 0;
     end
@@ -36,10 +40,11 @@ module testbench();
         errors = errors + 1;
       end
       vectornum = vectornum + 1;
-      if (testvectors[vectornum] === 5'bx) begin 
+      //if (testvectors[vectornum] === 5'bx) begin 
+      if (vectornum === 10) begin 
         $display("%d tests completed with %d errors", 
 	           vectornum, errors);
-        $stop;
+        $finish;
       end
     end
 endmodule

examples/verilog/fulladder/verilate

@@ -0,0 +1,5 @@
+#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
+#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
+#verilator --binary --top-module testbench fulladder.sv
+verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
+

sim/coverage-exclusions-rv64gc.do

@@ -186,7 +186,7 @@ set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM    & PMAAccessFault"]
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
 set line [GetLineNum ../src/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="] 
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line
-set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"] 
+set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"] 
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
 set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] 
 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
@@ -234,6 +234,12 @@ coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondr
 set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
 coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
 
+# Exclude system reset case in ebu
+set line [GetLineNum ../src/ebu/ebufsmarb.sv "BeatCounter\\("]
+coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
+set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
+coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
+
 # TLB not recently used never has all RU bits = 1 because it will then clear all to 0
 # This is a blunt instrument; perhaps there is a more graceful exclusion
 coverage exclude -srcfile priorityonehot.sv 

sim/verilate

@@ -8,9 +8,11 @@ basepath=$(dirname $0)/..
 #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
 for config in  rv64gc; do
     echo "$config simulating..."
-    if !($verilator --timescale "1ns/1ns" --timing --exe --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    # not working: -GTEST="arch64i"
+    if !($verilator --timescale "1ns/1ns" --timing --binary "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
+    ./obj_dir/Vtestbench 
 done
 echo "Verilation complete"

src/ifu/ifu.sv

@@ -369,11 +369,11 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  if (P.COMPRESSED_SUPPORTED) begin
+  if (P.COMPRESSED_SUPPORTED) begin: decomp
     logic IllegalCompInstrD;
     decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
-  end else begin  
+  end else begin: decomp
     assign InstrD = InstrRawD;
     assign IllegalIEUInstrD = IllegalBaseInstrD;
   end

src/lsu/align.sv

@@ -117,9 +117,9 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   always_comb begin
     case (CurrState)
-      STATE_READY: if (ValidSpillM & ~MemRWM[0])   NextState = STATE_SPILL;
+      STATE_READY: if (ValidSpillM & ~MemRWM[0])  NextState = STATE_SPILL;       // load spill
-                   else if(ValidSpillM & MemRWM[0])NextState = STATE_STORE_DELAY;
+                   else if(ValidSpillM)           NextState = STATE_STORE_DELAY; // store spill
-                   else                           NextState = STATE_READY;
+                   else                           NextState = STATE_READY;       // no spill
       STATE_SPILL: if(StallM)                     NextState = STATE_SPILL;
                    else                           NextState = STATE_READY;
       STATE_STORE_DELAY: NextState = STATE_SPILL;
@@ -131,7 +131,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY);
   assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM;
   assign SelStoreDelay = (CurrState == STATE_STORE_DELAY);  // *** Can this be merged into the PreLSURWM logic?
-  assign SpillStallM = SelSpillE | CurrState == STATE_STORE_DELAY;
+  assign SpillStallM = SelSpillE;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // Merge spilled data

src/mmu/pmachecker.sv

@@ -67,12 +67,12 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   assign Idempotent = (PBMemoryType == 2'b00) ? IdempotentRegion : (PBMemoryType == 2'b01);  
  
   // Atomic operations are only allowed on RAM
-  assign AtomicAllowed = SelRegions[1] | SelRegions[3] | SelRegions[5]; // exclusion-tag: unused-idempotent
+  assign AtomicAllowed = SelRegions[1] | SelRegions[3] | SelRegions[5]; // exclusion-tag: unused-atomic
   // Check if tightly integrated memories are selected
-  assign SelTIM = SelRegions[1] | SelRegions[2]; // exclusion-tag: unused-idempotent
+  assign SelTIM = SelRegions[1] | SelRegions[2]; // exclusion-tag: unused-tim
 
   // Detect access faults
-  assign PMAAccessFault          = (SelRegions[0]) & AccessRWXC | AtomicAccessM & ~AtomicAllowed;  
+  assign PMAAccessFault          = SelRegions[0] & AccessRWXC | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
   assign PMALoadAccessFaultM     = ReadAccessM    & PMAAccessFault;
   assign PMAStoreAmoAccessFaultM = (WriteAccessM | (|CMOpM))   & PMAAccessFault;

testbench/tests.vh

@@ -45,7 +45,7 @@ string tvpaths[] = '{
   string coverage64gc[] = '{
     `COVERAGE,
     "ieu",
-//    "tlbNAPOT",
+    "tlbNAPOT",
     "priv",
     "ebu",
     "csrwrites",
@@ -2114,7 +2114,7 @@ string arch64zbs[] = '{
     `WALLYTEST,
     "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
     "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
-    "rv32i_m/privilege/src/WALLY-cbom-01.S",
+//    "rv32i_m/privilege/src/WALLY-cbom-01.S",
     "rv32i_m/privilege/src/WALLY-cboz-01.S",
     "rv32i_m/privilege/src/WALLY-mie-01.S",
     "rv32i_m/privilege/src/WALLY-minfo-01.S",

tests/riscof/spike/spike_rv64gc_isa.yaml

@@ -1,7 +1,7 @@
 hart_ids: [0]
 hart0:
-#  ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
+#  ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
-  ISA: RV64IMAFDCSUZicsr_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
+  ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zbb_Zbc_Zbs # Zkbs_Zcb
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]