From 0e9e7d0a49262a201b3ef84e0623e3620db3cf0a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 29 Aug 2024 11:11:19 -0700 Subject: [PATCH 1/2] Fixed wallyTracer floating-point register FLEN --- testbench/common/wallyTracer.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 5676f6c13..98969c37f 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -52,7 +52,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [NUMREGS-1:0] rf_wb; logic [4:0] rf_a3; logic rf_we3; - logic [P.XLEN-1:0] frf[32]; + logic [P.FLEN-1:0] frf[32]; logic [`NUM_REGS-1:0] frf_wb; logic [4:0] frf_a4; logic frf_we4; From 4f8fedad2e4f6f7e12fbe6b4393f8d0112f1481f Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 30 Aug 2024 13:37:18 -0700 Subject: [PATCH 2/2] README update --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 39b5c6780..034aa2820 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # core-v-wally -Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor. +Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores. ![Wally block diagram](wallyriscvTopAll.png)