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Simplified performance counters

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This commit is contained in:
David Harris 2021-12-31 06:40:21 +00:00
parent 42df98bc6d
commit 9f24b4c969
9 changed files with 32 additions and 19 deletions
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2
wally-pipelined/regression/sim-wally-batch
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@ -1,3 +1,3 @@
vsim -c <<! vsim -c <<!
do wally-pipelined-batch.do rv64gc wally64priv do wally-pipelined-batch.do rv64gc imperas64i
! !

2
wally-pipelined/src/privileged/csr.sv
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@ -39,7 +39,7 @@ module csr #(parameter
input logic [`XLEN-1:0] PCM, SrcAM, input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD, input logic InstrValidM, FRegWriteM, LoadStallD,
input logic BPPredDirWrongM, input logic BPPredDirWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,

23
wally-pipelined/src/privileged/csrc.sv
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@ -31,7 +31,9 @@ module csrc #(parameter
MHPMCOUNTERBASE = 12'hB00, MHPMCOUNTERBASE = 12'hB00,
MHPMCOUNTERHBASE = 12'hB80, MHPMCOUNTERHBASE = 12'hB80,
HPMCOUNTERBASE = 12'hC00, HPMCOUNTERBASE = 12'hC00,
HPMCOUNTERHBASE = 12'hC80 HPMCOUNTERHBASE = 12'hC80,
TIME = 12'hC01,
TIMEH = 12'hC81
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic StallE, StallM, StallW, input logic StallE, StallM, StallW,
@ -48,7 +50,7 @@ module csrc #(parameter
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [63:0] MTIME_CLINT,
output logic [`XLEN-1:0] CSRCReadValM, output logic [`XLEN-1:0] CSRCReadValM,
output logic IllegalCSRCAccessM output logic IllegalCSRCAccessM
); );
@ -124,17 +126,26 @@ module csrc #(parameter
MCOUNTEREN_REGW[CounterNumM] && (!`S_SUPPORTED || PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin MCOUNTEREN_REGW[CounterNumM] && (!`S_SUPPORTED || PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
IllegalCSRCAccessM = 0; IllegalCSRCAccessM = 0;
if (`XLEN==64) begin // 64-bit counter reads if (`XLEN==64) begin // 64-bit counter reads
if (CSRAdrM >= MHPMCOUNTERBASE && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; // Veri lator doesn't realize this only occurs for XLEN=64
/* verilator lint_off WIDTH */
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
/* verilator lint_on WIDTH */
else if (CSRAdrM >= MHPMCOUNTERBASE && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERBASE && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; else if (CSRAdrM >= HPMCOUNTERBASE && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else begin else begin
CSRCReadValM = 0; CSRCReadValM = 0;
IllegalCSRCAccessM = 1; // requested CSR doesn't exist IllegalCSRCAccessM = 1; // requested CSR doesn't exist
end end
end else begin // 32-bit counter reads end else begin // 32-bit counter reads
if (CSRAdrM >= MHPMCOUNTERBASE && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; // Veri lator doesn't realize this only occurs for XLEN=32
else if (CSRAdrM >= HPMCOUNTERBASE && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; /* verilator lint_off WIDTH */
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
/* verilator lint_on WIDTH */
else if (CSRAdrM >= MHPMCOUNTERBASE && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERBASE && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
else if (CSRAdrM >= MHPMCOUNTERHBASE && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; else if (CSRAdrM >= MHPMCOUNTERHBASE && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
else if (CSRAdrM >= HPMCOUNTERHBASE && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; else if (CSRAdrM >= HPMCOUNTERHBASE && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
else begin else begin
CSRCReadValM = 0; CSRCReadValM = 0;
IllegalCSRCAccessM = 1; // requested CSR doesn't exist IllegalCSRCAccessM = 1; // requested CSR doesn't exist

4
wally-pipelined/src/privileged/privileged.sv
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@ -54,7 +54,7 @@ module privileged (
input logic LoadMisalignedFaultM, input logic LoadMisalignedFaultM,
input logic StoreMisalignedFaultM, input logic StoreMisalignedFaultM,
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [63:0] MTIME_CLINT,
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
@ -160,7 +160,7 @@ module privileged (
.InstrM, .PCM, .SrcAM, .InstrM, .PCM, .SrcAM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM,
.TimerIntM, .ExtIntM, .SwIntM, .TimerIntM, .ExtIntM, .SwIntM,
.MTIME_CLINT, .MTIMECMP_CLINT, .MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD, .InstrValidM, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,

3
wally-pipelined/src/uncore/clint.sv
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@ -36,7 +36,7 @@ module clint (
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
output logic [`XLEN-1:0] HREADCLINT, output logic [`XLEN-1:0] HREADCLINT,
output logic HRESPCLINT, HREADYCLINT, output logic HRESPCLINT, HREADYCLINT,
output logic [63:0] MTIME, MTIMECMP, output logic [63:0] MTIME,
output logic TimerIntM, SwIntM); output logic TimerIntM, SwIntM);
logic MSIP; logic MSIP;
@ -44,6 +44,7 @@ module clint (
logic [15:0] entry, entryd; logic [15:0] entry, entryd;
logic memwrite; logic memwrite;
logic initTrans; logic initTrans;
logic [63:0] MTIMECMP;
assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00); assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
// entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data

6
wally-pipelined/src/uncore/uncore.sv
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@ -59,7 +59,7 @@ module uncore (
input logic SDCCmdIn, input logic SDCCmdIn,
input logic [3:0] SDCDatIn, input logic [3:0] SDCDatIn,
output logic SDCCLK, output logic SDCCLK,
output logic [63:0] MTIME_CLINT, MTIMECMP_CLINT output logic [63:0] MTIME_CLINT
); );
logic [`XLEN-1:0] HWDATA; logic [`XLEN-1:0] HWDATA;
@ -120,11 +120,11 @@ module uncore (
.HWDATA, .HREADY, .HTRANS, .HWDATA, .HREADY, .HTRANS,
.HREADCLINT, .HREADCLINT,
.HRESPCLINT, .HREADYCLINT, .HRESPCLINT, .HREADYCLINT,
.MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .MTIME(MTIME_CLINT),
.TimerIntM, .SwIntM); .TimerIntM, .SwIntM);
end else begin : clint end else begin : clint
assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0; assign MTIME_CLINT = 0;
assign TimerIntM = 0; assign SwIntM = 0; assign TimerIntM = 0; assign SwIntM = 0;
end end
if (`PLIC_SUPPORTED == 1) begin : plic if (`PLIC_SUPPORTED == 1) begin : plic

4
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -30,7 +30,7 @@ module wallypipelinedhart (
input logic clk, reset, input logic clk, reset,
// Privileged // Privileged
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [63:0] MTIME_CLINT,
// Bus Interface // Bus Interface
input logic [`AHBW-1:0] HRDATA, input logic [`AHBW-1:0] HRDATA,
input logic HREADY, HRESP, input logic HREADY, HRESP,
@ -323,7 +323,7 @@ module wallypipelinedhart (
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.LoadMisalignedFaultM, .StoreMisalignedFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
.TimerIntM, .ExtIntM, .SwIntM, .TimerIntM, .ExtIntM, .SwIntM,
.MTIME_CLINT, .MTIMECMP_CLINT, .MTIME_CLINT,
.InstrMisalignedAdrM, .IEUAdrM, .InstrMisalignedAdrM, .IEUAdrM,
.SetFflagsM, .SetFflagsM,
// Trap signals from pmp/pma in mmu // Trap signals from pmp/pma in mmu

6
wally-pipelined/src/wally/wallypipelinedsoc.sv
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@ -67,7 +67,7 @@ module wallypipelinedsoc (
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; logic HRESP;
logic TimerIntM, SwIntM; // from CLINT logic TimerIntM, SwIntM; // from CLINT
logic [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic ExtIntM; // from PLIC logic ExtIntM; // from PLIC
logic [2:0] HADDRD; logic [2:0] HADDRD;
logic [3:0] HSIZED; logic [3:0] HSIZED;
@ -79,7 +79,7 @@ module wallypipelinedsoc (
// instantiate processor and memories // instantiate processor and memories
wallypipelinedhart hart(.clk, .reset, wallypipelinedhart hart(.clk, .reset,
.TimerIntM, .ExtIntM, .SwIntM, .TimerIntM, .ExtIntM, .SwIntM,
.MTIME_CLINT, .MTIMECMP_CLINT, .MTIME_CLINT,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
.HADDRD, .HSIZED, .HWRITED .HADDRD, .HSIZED, .HWRITED
@ -88,7 +88,7 @@ module wallypipelinedsoc (
uncore uncore(.HCLK, .HRESETn, uncore uncore(.HCLK, .HRESETn,
.HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT, .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
.HSELEXT, .HSELEXT,
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK

1
wally-pipelined/testbench/tests.vh
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@ -680,6 +680,7 @@ string imperas32f[] = '{
string imperas64i[] = '{ string imperas64i[] = '{
`IMPERASTEST, `IMPERASTEST,
"rv64i_m/I/I-DELAY_SLOTS-01", "002010",
"rv64i_m/I/ADD-01", "004010", "rv64i_m/I/ADD-01", "004010",
"rv64i_m/I/ADDI-01", "003010", "rv64i_m/I/ADDI-01", "003010",
"rv64i_m/I/ADDIW-01", "003010", "rv64i_m/I/ADDIW-01", "003010",