Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

.gitignore

@@ -76,7 +76,8 @@ synthDC/*.log
 synthDC/*.svf
 synthDC/runs/
 synthDC/newRuns
-synthDC/PPAruns
+synthDC/ppa/PPAruns
+synthDC/ppa/plots
 synthDC/plots/
 synthDC/runArchive
 synthDC/hdl

pipelined/src/cache/cache.sv

@@ -168,9 +168,9 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   else
     mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
       .d1(CacheBusWriteData),	.s(SetValid), .y(CacheWriteData));
-  mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
+  mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
-		.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
+		.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
-		.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
+		.d2({VictimTag, FlushAdr, {OFFSETLEN{1'b0}}}),
 		.s({SelFlush, SelEvict}), .y(CacheBusAdr));
 
   /////////////////////////////////////////////////////////////////////////////////////////////

pipelined/src/generic/priorityonehot.sv

@@ -39,9 +39,11 @@ module priorityonehot #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
 );
-  logic [N-1:0] nolower;
 
-  // create thermometer code mask
+  genvar i;
-  prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower));
+  assign y[0] = a[0];
-  assign y = a & nolower;
+  for (i=1; i<N; i++) begin:poh
+    assign y[i] = a[i] & ~|a[i-1:0];
+  end
+
 endmodule

pipelined/src/mmu/pmpadrdec.sv

@@ -39,7 +39,6 @@ module pmpadrdec (
   input  logic [7:0]       PMPCfg,
   input  logic [`XLEN-1:0] PMPAdr,
   input  logic             PAgePMPAdrIn,
-  input  logic             FirstMatch,
   output logic             PAgePMPAdrOut,
   output logic             Match, Active, 
   output logic             L, X, W, R
@@ -83,10 +82,10 @@ module pmpadrdec (
                  (AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch :
                  0;
 
-  assign L = PMPCfg[7] & FirstMatch;
+  assign L = PMPCfg[7];
-  assign X = PMPCfg[2] & FirstMatch;
+  assign X = PMPCfg[2];
-  assign W = PMPCfg[1] & FirstMatch;
+  assign W = PMPCfg[1];
-  assign R = PMPCfg[0] & FirstMatch;
+  assign R = PMPCfg[0];
   assign Active = |PMPCfg[4:3];
  endmodule
 

pipelined/src/mmu/pmpchecker.sv

@@ -67,16 +67,16 @@ module pmpchecker (
       .PMPAdr(PMPADDR_ARRAY_REGW),
       .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
       .PAgePMPAdrOut(PAgePMPAdr),
-      .FirstMatch, .Match, .Active, .L, .X, .W, .R);
+      .Match, .Active, .L, .X, .W, .R);
 
     priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
     // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
-    assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; 
+    assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
 
-    assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|X;
+    assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
-    assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM   & ~|W;
+    assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
-    assign PMPLoadAccessFaultM  = EnforcePMP & ReadAccessM    & ~|R;
+    assign PMPLoadAccessFaultM  = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
   end else begin: pmpchecker  // no checker
     assign PMPInstrAccessFaultF = 0;
     assign PMPLoadAccessFaultM = 0;

pipelined/srt/inttestgen.c

@@ -0,0 +1,83 @@
+/* testgen.c */
+
+/* Written 10/31/96 by David Harris
+
+   This program creates test vectors for mantissa component
+   of an IEEE floating point divider. 
+   */
+
+/* #includes */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+/* Constants */
+
+#define ENTRIES  10
+#define RANDOM_VECS 500
+
+/* Prototypes */
+
+void output(FILE *fptr, long a, long b, long r, long rem);
+void printhex(FILE *fptr, long x);
+double random_input(void);
+
+/* Main */
+
+void main(void)
+{
+  FILE *fptr;
+  long a, b, r, rem;
+  long list[ENTRIES] = {1, 3, 5, 18, 25, 33, 42, 65, 103, 255};
+  int i, j;
+
+  if ((fptr = fopen("inttestvectors","w")) == NULL) {
+    fprintf(stderr, "Couldn't write testvectors file\n");
+    exit(1);
+  }
+
+  for (i=0; i<ENTRIES; i++) {
+    b = list[i];
+    for (j=0; j<ENTRIES; j++) {
+      a = list[j];
+      r = a/b;
+      rem = a%b;
+      output(fptr, a, b, r, rem);
+    }
+  }
+  
+//   for (i = 0; i< RANDOM_VECS; i++) {
+//     a = random_input();
+//     b = random_input();
+//     r = a/b;
+//     output(fptr, a, b, r);
+//   }
+
+  fclose(fptr);
+}
+
+/* Functions */
+
+void output(FILE *fptr, long a, long b, long r, long rem)
+{
+  printhex(fptr, a);
+  fprintf(fptr, "_");
+  printhex(fptr, b);
+  fprintf(fptr, "_");
+  printhex(fptr, r);
+  fprintf(fptr, "_");
+  printhex(fptr, rem);
+  fprintf(fptr, "\n");
+}
+
+void printhex(FILE *fptr, long m)
+{
+    fprintf(fptr, "%016llx", m);
+}    
+
+double random_input(void)
+{
+  return 1.0 + rand()/32767.0;
+}
+  

pipelined/srt/srt-waves.do

@@ -1,3 +1,5 @@
 add wave -noupdate /testbench/*
 add wave -noupdate /testbench/srt/*
 add wave -noupdate /testbench/srt/otfc2/*
+add wave -noupdate /testbench/srt/preproc/*
+add wave -noupdate /testbench/srt/divcounter/*

pipelined/srt/srt.sv

@@ -48,8 +48,8 @@ module srt (
   input  logic       Signed, // Interpret integers as signed 2's complement
   input  logic       Int, // Choose integer inputs
   input  logic       Sqrt, // perform square root, not divide
-  output logic       rsign,
+  output logic       rsign, done,
-  output logic [`DIVLEN-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
+  output logic [`DIVLEN-1:0] Rem, Quot, // *** later handle integers
   output logic [`NE-1:0] rExp,
   output logic [3:0] Flags
 );
@@ -59,11 +59,10 @@ module srt (
   logic           calcSign;
   logic [`DIVLEN-1:0]  X, Dpreproc;
   logic [`DIVLEN+3:0]  WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
-  logic [`DIVLEN+2:0]  rp, rm;
+  logic [$clog2(`XLEN+1)-1:0] intExp, dur, calcDur;
-  logic [$clog2(`XLEN+1)-1:0] intExp;
   logic           intSign;
  
-  srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign);
+  srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, calcDur, intSign);
 
   // Top Muxes and Registers
   // When start is asserted, the inputs are loaded into the divider.
@@ -78,25 +77,25 @@ module srt (
   // Quotient Selection logic
   // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
   qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qm);
-  // Accumulate quotient digits in a shift register (now done in OTFC)
+
-  qacc #(`DIVLEN+3) qacc(clk, Start, qp, qz, qm, rp, rm);
   flopen #(`NE) expflop(clk, Start, calcExp, rExp);
   flopen #(1) signflop(clk, Start, calcSign, rsign);
+  flopen #(7) durflop(clk, Start, calcDur, dur);
+  
+  counter divcounter(clk, Start, dur, done);
 
   // Divisor Selection logic
-  inv dinv(D, Db);
+  assign Db = ~D;
   mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
 
   // Partial Product Generation
   csa    #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
   
-  otfc2  #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, QuotOTFC);
+  otfc2  #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
 
   expcalc expcalc(.XExp, .YExp, .calcExp);
 
   signcalc signcalc(.XSign, .YSign, .calcSign);
-
-  srtpostproc postproc(rp, rm, Quot);
 endmodule
 
 ////////////////
@@ -115,7 +114,7 @@ module srtpreproc (
   input  logic       Int, // Choose integer inputs
   input  logic       Sqrt, // perform square root, not divide
   output logic [`DIVLEN-1:0] X, D,
-  output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
+  output logic [$clog2(`XLEN+1)-1:0] intExp, dur, // Quotient integer exponent
   output logic       intSign // Quotient integer sign
 );
 
@@ -132,8 +131,8 @@ module srtpreproc (
   assign ExtraA = {PosA, {`EXTRAINTBITS{1'b0}}};
   assign ExtraB = {PosB, {`EXTRAINTBITS{1'b0}}};
 
-  assign PreprocA = ExtraA << zeroCntA;
+  assign PreprocA = ExtraA << (zeroCntA + 1);
-  assign PreprocB = ExtraB << zeroCntB;
+  assign PreprocB = ExtraB << (zeroCntB + 1);
   assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}};
   assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}};
 
@@ -142,6 +141,8 @@ module srtpreproc (
   assign D = Int ? PreprocB : PreprocY;
   assign intExp = zeroCntB - zeroCntA + 1;
   assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
+
+  assign dur = Int ? (intExp & {7{~intExp[6]}}) : (`DIVLEN + 2);
 endmodule
 
 /////////////////////////////////
@@ -179,38 +180,10 @@ module qsel2 ( // *** eventually just change to 4 bits
   assign #1 qm = magnitude & sign;
 endmodule
 
-//////////
-// qacc //
-//////////
-// To be replaced by OTFC
-module qacc #(parameter N=68) (
-  input  logic         clk, 
-  input  logic         req, 
-  input  logic         qp, qz, qm, 
-  output logic [N-1:0] rp, rm
-);
-
-  flopr #(N) rmreg(clk, req, {rm[N-2:0], qm}, rm);
-  flopr #(N) rpreg(clk, req, {rp[N-2:0], qp}, rp);
-/*  always @(posedge clk)
-    begin
-      if (req) 
-	begin
-	  rp <= #1 0;
-	  rm <= #1 0;
-	end
-      else 
-	begin
-	  rm <= #1 {rm[54:0], qm};
-	  rp <= #1 {rp[54:0], qp};
-	end
-    end */
-endmodule
-
 ///////////////////////////////////
 // On-The-Fly Converter, Radix 2 //
 ///////////////////////////////////
-module otfc2 #(parameter N=65) (
+module otfc2 #(parameter N=64) (
   input  logic         clk,
   input  logic         Start,
   input  logic         qp, qz, qm,
@@ -254,13 +227,29 @@ module otfc2 #(parameter N=65) (
 
 endmodule
 
-/////////
+/////////////
-// inv //
+// counter //
-/////////
+/////////////
-module inv(input  logic [`DIVLEN+3:0] in, 
+module counter(input  logic clk, 
-           output logic [`DIVLEN+3:0] out);
+               input  logic req, 
+               input  logic [$clog2(`XLEN+1)-1:0] dur,
+               output logic done);
+ 
+   logic    [$clog2(`XLEN+1)-1:0]  count;
 
-  assign #1 out = ~in;
+  // This block of control logic sequences the divider
+  // through its iterations.  You may modify it if you
+  // build a divider which completes in fewer iterations.
+  // You are not responsible for the (trivial) circuit
+  // design of the block.
+
+  always @(posedge clk)
+    begin
+      if      (count == dur) done <= #1 1;
+      else if (done | req) done <= #1 0;	
+      if (req) count <= #1 0;
+      else     count <= #1 count+1;
+    end
 endmodule
 
 //////////
@@ -323,43 +312,4 @@ module signcalc(
 
   assign calcSign = XSign ^ YSign;
 
-endmodule
+endmodule
-
-////////////////////
-// Postprocessing //
-////////////////////
-module srtpostproc (
-  input  [`DIVLEN+2:0] rp, rm,
-  output [`DIVLEN-1:0] Quot
-);
-
-  //assign Quot = rp - rm;
-  finaladd #(`DIVLEN+3) finaladd(rp, rm, Quot);
-endmodule
-
-//////////////
-// finaladd //
-//////////////
-module finaladd #(parameter N=68) (
-  input  logic [N-1:0] rp, rm, 
-  output logic [N-4:0] r
-);
-
-  logic   [N-1:0] diff;
-
-  // this magic block performs the final addition for you
-  // to convert the positive and negative quotient digits
-  // into a normalized mantissa.  It returns the 52 bit
-  // mantissa after shifting to guarantee a leading 1.
-  // You can assume this block operates in one cycle
-  // and do not need to budget it in your area and power
-  // calculations.
-	
-  // Since no rounding is performed, the result may be too 
-  // small by one unit in the least significant place (ulp).
-  // The checker ignores such an error.
-
-  assign #1 diff = rp - rm;
-  assign #1 r = diff[N-1] ? diff[N-2:2] : diff[N-3:1];
-endmodule
-

pipelined/srt/testbench.sv

@@ -3,26 +3,26 @@
 /////////////
 // counter //
 /////////////
-module counter(input  logic clk, 
+// module counter(input  logic clk, 
-               input  logic req, 
+//                input  logic req, 
-               output logic done);
+//                output logic done);
  
-   logic    [7:0]  count;
+//    logic    [7:0]  count;
 
-  // This block of control logic sequences the divider
+//   // This block of control logic sequences the divider
-  // through its iterations.  You may modify it if you
+//   // through its iterations.  You may modify it if you
-  // build a divider which completes in fewer iterations.
+//   // build a divider which completes in fewer iterations.
-  // You are not responsible for the (trivial) circuit
+//   // You are not responsible for the (trivial) circuit
-  // design of the block.
+//   // design of the block.
 
-  always @(posedge clk)
+//   always @(posedge clk)
-    begin
+//     begin
-      if      (count == `DIVLEN + 2) done <= #1 1;
+//       if      (count == `DIVLEN + 2) done <= #1 1;
-      else if (done | req) done <= #1 0;	
+//       else if (done | req) done <= #1 0;	
-      if (req) count <= #1 0;
+//       if (req) count <= #1 0;
-      else     count <= #1 count+1;
+//       else     count <= #1 count+1;
-    end
+//     end
-endmodule
+// endmodule
 
 ///////////
 // clock //
@@ -42,21 +42,23 @@ module testbench;
   logic              clk;
   logic              req;
   logic              done;
+  logic              Int;
   logic [63:0]       a, b;
   logic [51:0]       afrac, bfrac;
   logic [10:0]       aExp, bExp;
   logic              asign, bsign;
-  logic [51:0]       r, rOTFC;
+  logic [51:0]       r;
-  logic [`DIVLEN-1:0]  Quot, QuotOTFC;
+  logic [63:0]       rInt;
-  logic [54:0]       rp, rm;   // positive quotient digits
+  logic [`DIVLEN-1:0]  Quot;
  
   // Test parameters
   parameter MEM_SIZE = 40000;
-  parameter MEM_WIDTH = 64+64+64;
+  parameter MEM_WIDTH = 64+64+64+64;
  
-  `define memr  63:0
+  `define memrem  63:0
-  `define memb  127:64
+  `define memr  127:64
-  `define mema  191:128
+  `define memb  191:128
+  `define mema  255:192
 
   // Test logicisters
   logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE];  // Space for input file
@@ -67,18 +69,20 @@ module testbench;
   logic        rsign;
   integer testnum, errors;
 
+  assign Int = 1'b1;
+
   // Divider
   srt srt(.clk, .Start(req), 
                 .Stall(1'b0), .Flush(1'b0), 
                 .XExp(aExp), .YExp(bExp), .rExp,
                 .XSign(asign), .YSign(bsign), .rsign,
                 .SrcXFrac(afrac), .SrcYFrac(bfrac), 
-                .SrcA('0), .SrcB('0), .Fmt(2'b00), 
+                .SrcA(a), .SrcB(b), .Fmt(2'b00), 
-                .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), 
+                .W64(1'b1), .Signed(1'b0), .Int, .Sqrt(1'b0), 
-                .Quot, .QuotOTFC, .Rem(), .Flags());
+                .Quot, .Rem(), .Flags(), .done);
 
   // Counter
-  counter counter(clk, req, done);
+  // counter counter(clk, req, done);
 
 
     initial
@@ -94,7 +98,7 @@ module testbench;
     begin
       testnum = 0; 
       errors = 0;
-      $readmemh ("testvectors", Tests);
+      $readmemh ("inttestvectors", Tests);
       Vec = Tests[testnum];
       a = Vec[`mema];
       {asign, aExp, afrac} = a;
@@ -102,7 +106,7 @@ module testbench;
       {bsign, bExp, bfrac} = b;
       nextr = Vec[`memr];
       r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
-      rOTFC = QuotOTFC[(`DIVLEN - 1):(`DIVLEN - 52)];
+      rInt = Quot;
       req <= #5 1;
     end
   
@@ -111,45 +115,54 @@ module testbench;
   always @(posedge clk)
     begin
       r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
-      rOTFC = QuotOTFC[(`DIVLEN - 1):(`DIVLEN - 52)];
+      rInt = Quot;
-      if (done) 
+      if (done) begin
-	begin
+        if (~Int) begin
-	  req <= #5 1;
+        req <= #5 1;
-    diffp = correctr[51:0] - r;
+        diffp = correctr[51:0] - r;
-    diffn = r - correctr[51:0];
+        diffn = r - correctr[51:0];
-	  if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
+        if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
-	    begin
+          begin
-	      errors = errors+1;
+            errors = errors+1;
-	      $display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);
+            $display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);
-	      $display("failed\n");
+            $display("failed\n");
-	      $stop;
+            $stop;
-	    end
+          end
-    if (r !== rOTFC) // Check if OTFC works
+        if (afrac === 52'hxxxxxxxxxxxxx)
-      begin
+          begin
-        errors = errors+1;
+            $display("%d Tests completed successfully", testnum);
-        $display("OTFC is %h, should be %h\n", rOTFC, r);
+            $stop;
-        $display("failed\n");
+          end
-        // $stop;
+        end else begin
+          req <= #5 1;
+          diffp = correctr[63:0] - rInt;
+          diffn = rInt - correctr[63:0];
+          if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
+            begin
+              errors = errors+1;
+              $display("result was %h, should be %h %h %h\n", rInt, correctr, diffn, diffp);
+              $display("failed\n");
+              $stop;
+            end
+        if (afrac === 52'hxxxxxxxxxxxxx)
+          begin
+            $display("%d Tests completed successfully", testnum);
+            $stop;
+          end
+	      end
       end
-	  if (afrac === 52'hxxxxxxxxxxxxx)
+    if (req) begin
-	    begin
+      req <= #5 0;
- 	      $display("%d Tests completed successfully", testnum);
+      correctr = nextr;
-	      $stop;
+      testnum = testnum+1;
-	    end
+      Vec = Tests[testnum];
-	end
+      $display("a = %h  b = %h",a,b);
-      if (req) 
+      a = Vec[`mema];
-	begin
+      {asign, aExp, afrac} = a;
-	  req <= #5 0;
+      b = Vec[`memb];
-	  correctr = nextr;
+      {bsign, bExp, bfrac} = b;
-	  testnum = testnum+1;
+      nextr = Vec[`memr];
-	  Vec = Tests[testnum];
+    end
-	  $display("a = %h  b = %h",a,b);
-    a = Vec[`mema];
-    {asign, aExp, afrac} = a;
-    b = Vec[`memb];
-    {bsign, bExp, bfrac} = b;
-    nextr = Vec[`memr];
-	end
     end
  
 endmodule

synthDC/Makefile

@@ -5,8 +5,8 @@ NAME := synth
 
 # defaults
 export DESIGN ?= wallypipelinedcore
-export FREQ ?= 3402
+export FREQ ?= 3000
-export CONFIG ?= rv32e
+export CONFIG ?= rv32gc
 # sky130 and sky90 presently supported
 export TECH ?= tsmc28
 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient
@@ -14,7 +14,7 @@ export TECH ?= tsmc28
 export MAXCORES ?= 4
 # MAXOPT turns on flattening, boundary optimization, and retiming
 # The output netlist is hard to interpret, but significantly better PPA
-export MAXOPT ?= 0
+export MAXOPT ?= 1
 export DRIVE ?= FLOP
 
 time := $(shell date +%F-%H-%M)

synthDC/oldBestSynths.csv

@@ -1,113 +0,0 @@
-Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (fJ)
-priorityencoder,sky90,8,7994,0.12495882036527395,60.760001,44.346,13.42057730723042
-priorityencoder,sky90,16,5761,0.16976997552508244,136.220003,77.243,21.28915493084534
-priorityencoder,sky90,32,4776,0.20887023450586265,379.260006,246.78,50.06619521105528
-priorityencoder,sky90,64,4096,0.244021625,794.780014,364.853,72.71844425000002
-priorityencoder,sky90,128,3409,0.2933331557641537,1602.300031,610.009,126.1332569785861
-add,sky90,8,3652,0.2733695629791895,245.000005,139.276,101.6934774282585
-add,sky90,16,2931,0.33991248447628797,623.280012,352.919,268.5308627362675
-add,sky90,32,2420,0.4132191404958678,1330.840024,582.809,520.6561170247934
-add,sky90,64,2139,0.4674681813931744,2781.240054,1050.0,939.1435764188874
-add,sky90,128,1885,0.5304949787798409,6186.740118,2230.0,2147.9741690795754
-csa,sky90,8,5740,0.16671402787456446,290.080006,207.654,143.04063591637635
-csa,sky90,16,5984,0.16522529946524064,588.000011,322.135,321.19798216042784
-csa,sky90,32,5740,0.16671402787456446,1160.320023,826.559,570.4954033867597
-csa,sky90,64,5984,0.16522529946524064,2469.600048,1440.0,1354.3517797165773
-csa,sky90,128,5984,0.16522529946524064,4897.060095,2990.0,2649.0572263262034
-shiftleft,sky90,8,4321,0.23108991020597083,250.880004,181.951,70.25133270261513
-shiftleft,sky90,16,3355,0.29803959314456036,666.400006,558.433,195.51397310283156
-shiftleft,sky90,32,2500,0.39945200000000003,1400.420023,738.137,368.29474400000004
-shiftleft,sky90,64,2203,0.45385946391284615,3914.120062,2680.0,1144.633567988198
-shiftleft,sky90,128,1907,0.5242938489774515,9192.400136,6080.0,2900.3935725432616
-comparator,sky90,8,4829,0.2066692116380203,198.940004,136.459,48.56726473493477
-comparator,sky90,16,4014,0.24886605181863478,355.740006,188.666,62.714245058295965
-comparator,sky90,32,3596,0.27763876307007784,697.760013,316.793,109.38967264961067
-comparator,sky90,64,3129,0.31954192361776923,1372.980026,508.393,204.82637303899006
-comparator,sky90,128,2682,0.37267507755406415,2836.120055,772.571,463.6077964772558
-flop,sky90,8,10,0.1143419999999935,133.279999,64.8145,0.22163481569998741
-flop,sky90,16,10,0.1143419999999935,266.5599975,129.629,0.4426750529999749
-flop,sky90,32,10,0.1143419999999935,533.119995,259.258,0.88306326599995
-flop,sky90,64,10,0.1143419999999935,1066.23999,520.0,1.7717864609998994
-flop,sky90,128,10,0.1143419999999935,2132.4799805,1035.0,3.537741479999799
-mux2,sky90,1,11806,0.08300869354565475,13.72,12.3,3.8183999031001186
-mux2,sky90,8,5280,0.1887229393939394,63.700001,23.506,19.476207345454547
-mux2,sky90,16,4815,0.20207331983385254,119.560002,32.354,37.76750347694705
-mux2,sky90,32,5000,0.19989700000000002,374.360008,259.372,136.72954800000002
-mux2,sky90,64,4060,0.24566741871921183,514.50001,165.954,163.6145008669951
-mux2,sky90,128,4004,0.24974824975024976,1302.420025,767.078,466.52973053346653
-mux4,sky90,1,7687,0.12838276193573567,28.420001,22.994,6.3164318872381955
-mux4,sky90,8,4655,0.21455177121374866,159.740002,86.462,42.03069198077337
-mux4,sky90,16,4452,0.22313914914645103,392.0,398.313,103.09028690566036
-mux4,sky90,32,3802,0.2622634634402946,465.500009,150.568,139.26189908679646
-mux4,sky90,64,3699,0.2695173360367667,877.100017,304.149,274.9076827575021
-mux4,sky90,128,3166,0.3157249696778269,1984.500039,725.267,569.5678452987997
-mux8,sky90,1,5763,0.17009673572791947,70.560001,49.874,12.31500366670137
-mux8,sky90,8,3577,0.2789168803466592,287.140006,116.648,60.83177160360637
-mux8,sky90,16,3419,0.2915101822170225,588.000006,280.193,150.71076420620065
-mux8,sky90,32,3155,0.3146512107765452,1237.740008,639.983,323.14679346751194
-mux8,sky90,64,3020,0.33032882781456957,2207.940042,730.503,445.61358872185434
-mux8,sky90,128,2666,0.37501377344336084,3761.240072,1460.0,854.281375903976
-mult,sky90,8,1310,0.7631557786259543,2194.220041,1440.0,1420.996059801527
-mult,sky90,16,997,1.0029260270812437,7519.540137,4940.0,6375.600754155466
-mult,sky90,32,763,1.3106129895150722,25200.700446,14900.0,24931.79089954522
-mult,sky90,64,632,1.5822664810126583,86011.661365,42600.0,88845.84517534176
-mult,sky90,128,524,1.9083759465648855,296198.144128,114000.0,273311.87793918326
-mux2d,sky90,1,13217,0.07565913467503972,19.6,18.562,6.03759894706817
-mux4d,sky90,1,9701,0.10307715647871353,51.940001,49.18,13.626800086485927
-mux8d,sky90,1,7099,0.1341249105507818,85.260001,40.078,14.405015393153965
-priorityencoder,tsmc28,8,31306,0.03191275857663067,8.316,34.836,1.713715135565067
-priorityencoder,tsmc28,16,21202,0.04705136175832468,21.294,73.912,3.815865438600132
-priorityencoder,tsmc28,32,16453,0.060740189205615996,62.118,205.801,9.439025402552724
-priorityencoder,tsmc28,64,13786,0.07244435673872045,137.088001,428.365,18.328422254896275
-priorityencoder,tsmc28,128,11439,0.0874122290410001,315.252,980.365,40.908923191188045
-add,tsmc28,8,13787,0.07226709545223761,33.012,176.194,12.328766484151734
-add,tsmc28,16,11520,0.08680155555555555,90.972001,475.452,33.67900355555555
-add,tsmc28,32,9810,0.1019177991845056,209.286002,1060.0,81.43232154841998
-add,tsmc28,64,8203,0.12186861952944045,392.616003,1800.0,142.34254761038645
-add,tsmc28,128,7210,0.13869425520110956,868.140006,4090.0,331.3405756754508
-csa,tsmc28,8,23865,0.04077636748376283,49.392,473.393,20.91827651917033
-csa,tsmc28,16,23865,0.04077636748376283,98.783999,946.879,41.75500030337314
-csa,tsmc28,32,23865,0.04077636748376283,197.567999,1890.0,83.30611876932745
-csa,tsmc28,64,23865,0.04077636748376283,395.135998,3790.0,166.5306848036874
-csa,tsmc28,128,23865,0.04077636748376283,790.271996,7570.0,333.1021459748586
-shiftleft,tsmc28,8,15183,0.06578013640255549,48.384,333.876,15.51753417736284
-shiftleft,tsmc28,16,11800,0.0847177627118644,130.788,613.549,33.71766955932203
-shiftleft,tsmc28,32,9587,0.10430391697089808,384.803997,1940.0,101.80062296359652
-shiftleft,tsmc28,64,8269,0.12088260744951022,967.427998,4980.0,272.83204501354453
-shiftleft,tsmc28,128,7023,0.14238329232521713,1836.953994,8670.0,566.543120162039
-comparator,tsmc28,8,17054,0.05854826984871585,32.256,160.477,8.752966342383019
-comparator,tsmc28,16,13709,0.07280278080093369,48.132,204.944,11.852292714392004
-comparator,tsmc28,32,12136,0.08238147264337507,146.16,623.674,35.50641470929466
-comparator,tsmc28,64,10862,0.09205807659731172,291.312,1240.0,69.41178975437303
-comparator,tsmc28,128,9371,0.10671119720414043,558.432,2400.0,127.9467254477644
-flop,tsmc28,8,10,0.048889000000002625,15.12,78.6345,0.013320296940000717
-flop,tsmc28,16,10,0.048889000000002625,30.24,157.29,0.026541838100001425
-flop,tsmc28,32,10,0.048889000000002625,60.4799995,314.5805,0.05332812120000287
-flop,tsmc28,64,10,0.048889000000002625,120.959999,630.0,0.10640935295000573
-flop,tsmc28,128,10,0.048889000000002625,241.919998,1260.0,0.21305826200001143
-mux2,tsmc28,1,50000,0.019658000000000002,2.142,15.112,0.5917058000000001
-mux2,tsmc28,8,29041,0.033768075961571574,16.884,113.726,5.335356001928308
-mux2,tsmc28,16,19059,0.05221864998163597,15.75,88.448,5.133093293194816
-mux2,tsmc28,32,17903,0.05585556035301346,32.130001,171.146,9.897605294553983
-mux2,tsmc28,64,18546,0.05385698274560552,90.846,517.414,27.359347234767604
-mux2,tsmc28,128,16594,0.0601057455706882,184.968,1150.0,58.603101931421
-mux4,tsmc28,1,26255,0.03808798324128737,5.292,41.928,1.7101504475338032
-mux4,tsmc28,8,18130,0.05509219801434087,27.971999,133.963,8.021424030888031
-mux4,tsmc28,16,16440,0.06065625060827251,39.438,185.149,12.373875124087593
-mux4,tsmc28,32,15168,0.0658052700421941,69.174,324.969,23.229260324894515
-mux4,tsmc28,64,13915,0.07180589399928135,137.465999,648.086,45.59674268954365
-mux4,tsmc28,128,13089,0.07639603056001222,296.603997,1440.0,94.50188980273512
-mux8,tsmc28,1,16320,0.05991150980392156,7.182,38.342,1.8428780415686272
-mux8,tsmc28,8,12885,0.07750962359332557,44.856,215.13,11.90547818393481
-mux8,tsmc28,16,12256,0.08154268929503918,121.841998,521.624,25.93057519582246
-mux8,tsmc28,32,11695,0.08537362676357418,168.21,815.694,46.35787933262078
-mux8,tsmc28,64,11000,0.0907930909090909,304.037999,1490.0,81.89536799999999
-mux8,tsmc28,128,10464,0.09547474923547401,664.775992,2850.0,153.04602302446486
-mult,tsmc28,8,5000,0.19998100000000002,444.150001,3260.0,306.970835
-mult,tsmc28,16,3819,0.26184265147944485,1634.472002,11800.0,1455.3214569227544
-mult,tsmc28,32,2973,0.3363555785401951,5141.430011,36900.0,5416.333881232761
-mult,tsmc28,64,2390,0.4184090418410042,16045.092071,109000.0,18545.980779602512
-mult,tsmc28,128,1868,0.5353279057815846,44272.49428,262000.0,50011.4036139272
-mux2d,tsmc28,1,51887,0.018931650182126544,3.276,26.574,0.9106123737602868
-mux4d,tsmc28,1,32558,0.03008041734750292,4.158,30.464,1.2543534033908719
-mux8d,tsmc28,1,21936,0.045586162654996355,20.664,171.151,6.614552201239972

synthDC/ppa/ppaAnalyze.py

@@ -245,7 +245,7 @@ def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, colo
         ax.add_artist(ax.legend(handles=fullLeg, loc=legLoc))
         titleStr = "  (target  " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)"
         ax.set_title(module + titleStr)
-        plt.savefig('./plots/PPA/'+ module + '_' + var + '.png')
+        plt.savefig('.plots/'+ module + '_' + var + '.png')
         # plt.show()
     return r2
 
@@ -550,7 +550,7 @@ def plotPPA(mod, freq=None, norm=True, aleOpt=False):
 
     if freq != 10: 
         n = 'normalized' if norm else 'unnormalized'
-        saveStr = './plots/PPA/'+ n + '/' + mod + '.png'
+        saveStr = './plots/'+ n + '/' + mod + '.png'
         plt.savefig(saveStr)
     # plt.show()
 
@@ -563,7 +563,7 @@ def makeLineLegend():
     fullLeg += [lines.Line2D([0], [0], color='green', label='sky90', marker='o')]
     fullLeg += [lines.Line2D([0], [0], color='red', label='combined', marker='_')]
     fig.legend(handles=fullLeg, ncol=5, handlelength=1.4, loc='center') 
-    saveStr = './plots/PPA/legend.png'
+    saveStr = './plots/legend.png'
     plt.savefig(saveStr)
 
 def muxPlot(fits='clsgn', norm=True):
@@ -616,7 +616,7 @@ def muxPlot(fits='clsgn', norm=True):
     ax.set_title('mux timing')
     
     ax.legend(handles = fullLeg)
-    plt.savefig('./plots/PPA/mux.png')
+    plt.savefig('./plots/mux.png')
 
 def stdDevError():
     for var in ['delay', 'area', 'lpower', 'denergy']:

synthDC/scripts/synth.tcl

@@ -102,7 +102,8 @@ set_critical_range [expr $my_period*0.05] $current_design
 
 # Partitioning - flatten or hierarchically synthesize
 if { $maxopt == 1 } {
-    ungroup -all -flatten -simple_names
+    ungroup -all -simple_names
+    # -flatten 
 }
 
 # Set input pins except clock

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output

@@ -1,18 +1,16 @@
-00000000 # test reset to zero
+00000000 # reset to zero tests: input_val
-00000000
+00000000 #  input_en
-00000000 # output_en
+00000000 #  output_en
-00000000 # output_val
+00000000 #  output_val
-00000000 # rise_ie
+00000000 #  rise_ie
-00000000 # rise_ip
+00000000 #  fall_ie
-00000000 # fall_ie
+00000000 #  low_ie
-00000000 # fall_ip
+00000000 #  high_ie
-00000000 # high_ie
+00000000 #  rise_ip
-00000000 # high_ip
+00000000 #  fall_ip
-00000000 # low_ie
+00000000 #  high_ip
-ffffffff # low_ip
+ffffffff #  low_ip
-00000000 # iof_en
+00000000 #  out_xor
-00000000 # iof_sel
-00000000 # out_xor
 A5A5A5A5 # test output pins
 5A5AFFFF
 00000000 # test input enables
@@ -32,5 +30,12 @@ A5FA0000 #   high_ip
 00000000 #   MIP = 0
 00000000 #   MIP = 0
 00000000 #   MIP = 0
-00000800 #  Test interrupts can be enabled and triggered: MEIP set
+00000800 # Test interrupts can be enabled and triggered: MEIP set from high_ie
 00000000 #   MEIP = 0
+00000800 #  MEIP set from low_ie
+00000000 #   MEIP = 0
+00000800 #  MEIP set from rise_ie
+00000000 #   MEIP = 0
+00000800 #  MEIP set from fall_ie
+00000000 #   MEIP = 0
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S

@@ -91,13 +91,3 @@ test_cases:
 .4byte 0x0, 0x00000080, readmip_test        # mtip should be set
 
 .4byte 0x0, 0x0, terminate_test # terminate tests
-
-# =========== Experimental mtime counting test ===========
-
-# .4byte mtimecmph, 0xFFFFFFFF, write32_test  # make sure mtip isn't set until ready
-# .4byte mtimeh, 0x0FFFFFFF, write32_test     # write near max value to mtimeh
-# .4byte mtime, 0x00000000, write32_test      # write small value to mtime
-# .4byte 0x0, 0x000000000, readmip_test       # mtip should be zero
-# .4byte mtimecmp, 0x00000001, write32_test   # write slightly larger value than mtime to test mtime counting
-# .4byte mtimecmph, 0x0FFFFFFF, write32_test  # write same value as mtimeh to test mtime counting
-# .4byte 0x0, 0x00000080, readmip_test        # mtip should be set since it has been at least two cycles

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S

@@ -75,15 +75,13 @@ test_cases:
 .4byte output_en, 0x00000000, read32_test   # output_en reset to zero
 .4byte output_val, 0x00000000, read32_test  # output_val reset to zero
 .4byte rise_ie, 0x00000000, read32_test     # rise_ie reset to zero
-.4byte rise_ip, 0x00000000, read32_test     # rise_ip reset to zero
 .4byte fall_ie, 0x00000000, read32_test     # fall_ie reset to zero
-.4byte fall_ip, 0x00000000, read32_test     # fall_ip reset to zeros 
 .4byte high_ie, 0x00000000, read32_test     # high_ie reset to zero
-.4byte high_ip, 0x00000000, read32_test     # high_ip reset to zero
 .4byte low_ie, 0x00000000, read32_test      # low_ie reset to zero
-.4byte low_ip, 0xffffffff, read32_test      # low_ip reset to ones (input_val is zero)
+.4byte rise_ip, 0x00000000, read32_test     # rise_ip reset to zero
-.4byte iof_en, 0x00000000, read32_test      # iof_en reset to zero
+.4byte fall_ip, 0x00000000, read32_test     # fall_ip reset to zero
-.4byte iof_sel, 0x00000000, read32_test     # iof_sel reset to zero
+.4byte high_ip, 0x00000000, read32_test     # high_ip reset to zero
+.4byte low_ip, 0xffffffff, read32_test      # low_ip reset to ones since all zeroes
 .4byte out_xor, 0x00000000, read32_test     # out_xor reset to zero
 
 # =========== Test output and input pins ===========
@@ -120,7 +118,7 @@ SETUP_PLIC
 .4byte fall_ip, 0x00000000, read32_test             # check pending fall interrupts
 .4byte output_val, 0x5BAA000F, write32_test         # change output pattern to check rise/fall interrupts
 .4byte input_val, 0xA4AA0000, read32_test           # check new output matches expected output
-.4byte high_ip, 0xA5FA00000, read32_test            # high interrupt pending *** (is this correct?)
+.4byte high_ip, 0xA5FA0000, read32_test             # high interrupt pending
 .4byte low_ip, 0x5BF5FFFF, read32_test              # low interrupt pending should be opposite high for enabled pins
 .4byte rise_ip, 0x00A00000, read32_test             # check for changed bits (rising)
 .4byte fall_ip, 0x01500000, read32_test             # check for changed bits (falling)
@@ -137,11 +135,23 @@ SETUP_PLIC
 .4byte fall_ie, 0x00010000, write32_test            # enable fall interrupt on bit 16, no pending interrupt
 .4byte 0x0, 0x00000000, readmip_test                # No external interrupt should be pending
 
-# =========== Test interrupts can be enabled and triggered
+# =========== Test interrupts can be enabled and triggered ===========
 
 .4byte high_ie, 0x00020000, write32_test            # enable high interrupt on bit 17, which is pending
 .4byte 0x0, 0x00000800, readmip_test                # MEIP should be raised
-.4byte high_ie, 0x00000000, write32_test             # disable high interrupt on bit 17, which is pending
+.4byte high_ie, 0x00000000, write32_test            # disable high interrupt on bit 17
+.4byte 0x0, 0x00000000, readmip_test                # MEIP should be released
+.4byte low_ie, 0x00010000, write32_test             # enable low interrupt on bit 16, which is pending
+.4byte 0x0, 0x00000800, readmip_test                # MEIP should be raised
+.4byte low_ie, 0x00000000, write32_test             # disable low interrupt on bit 16
+.4byte 0x0, 0x00000000, readmip_test                # MEIP should be released
+.4byte rise_ie, 0x00200000, write32_test            # enable rise interrupt on bit 21, which is pending
+.4byte 0x0, 0x00000800, readmip_test                # MEIP should be raised
+.4byte rise_ie, 0x00000000, write32_test            # disable rise interrupt on bit 21, which is pending
+.4byte 0x0, 0x00000000, readmip_test                # MEIP should be released
+.4byte fall_ie, 0x01000000, write32_test            # enable high interrupt on bit 24, which is pending
+.4byte 0x0, 0x00000800, readmip_test                # MEIP should be raised
+.4byte high_ie, 0x00000000, write32_test            # disable high interrupt on bit 24, which is pending
 .4byte 0x0, 0x00000000, readmip_test                # MEIP should be released
 
 .4byte 0x0, 0x0, terminate_test # terminate tests