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https://github.com/openhwgroup/cvw
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Fixed sutble RAS bug when the stack size was not a power of 2.
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@ -27,8 +27,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module RASPredictor import cvw::*; #(parameter cvw_t P,
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parameter StackSize = 16 )(
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module RASPredictor import cvw::*; #(parameter cvw_t P)(
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
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@ -41,10 +40,10 @@ module RASPredictor import cvw::*; #(parameter cvw_t P,
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);
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logic CounterEn;
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localparam Depth = $clog2(StackSize);
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localparam Depth = $clog2(P.RAS_SIZE);
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logic [Depth-1:0] NextPtr, Ptr, P1, M1, IncDecPtr;
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logic [StackSize-1:0] [P.XLEN-1:0] memory;
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logic [P.RAS_SIZE-1:0] [P.XLEN-1:0] memory;
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integer index;
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logic PopF;
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@ -76,14 +75,17 @@ module RASPredictor import cvw::*; #(parameter cvw_t P,
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assign P1 = 1;
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assign M1 = '1; // -1
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mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
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assign NextPtr = Ptr + IncDecPtr;
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logic [Depth-1:0] Sum;
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assign Sum = Ptr + IncDecPtr;
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assign NextPtr = Sum == P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
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//assign NextPtr = Ptr + IncDecPtr;
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flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
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// RAS must be reset.
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always_ff @ (posedge clk) begin
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if(reset) begin
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for(index=0; index<StackSize; index++)
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for(index=0; index<P.RAS_SIZE; index++)
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memory[index] <= {P.XLEN{1'b0}};
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end else if(PushE) begin
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memory[NextPtr] <= #1 PCLinkE;
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