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Merge pull request #942 from ross144/main

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Improved automated support for FPGAs
This commit is contained in:
David Harris 2024-09-04 17:57:01 -07:00 committed by GitHub
commit 9eb7869205
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GPG Key ID: B5690EEEBB952194
14 changed files with 247 additions and 40 deletions
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8
config/derivlist.txt
View File

@ -54,11 +54,17 @@ UNCORE_RAM_RANGE 64'h1FFF
BOOTROM_RANGE 64'hFFF BOOTROM_RANGE 64'hFFF
EXT_MEM_SUPPORTED 1 EXT_MEM_SUPPORTED 1
EXT_MEM_BASE 64'h80000000 EXT_MEM_BASE 64'h80000000
EXT_MEM_RANGE 64'h0FFFFFFF EXT_MEM_RANGE 64'h7FFFFFFF
SDC_SUPPORTED 1 SDC_SUPPORTED 1
PLIC_SDC_ID 32'd20 PLIC_SDC_ID 32'd20
BPRED_SIZE 32'd12 BPRED_SIZE 32'd12
deriv fpgaArtyA7 fpga
EXT_MEM_RANGE 64'h0FFFFFFF
deriv fpgavcu108 fpga
EXT_MEM_RANGE 64'h7FFFFFFF
# temporary spitest configuration # temporary spitest configuration
deriv spitest rv64gc deriv spitest rv64gc
UNCORE_RAM_RANGE 64'h0FFFFFFF UNCORE_RAM_RANGE 64'h0FFFFFFF

18
fpga/constraints/constraints-vcu108.xdc
View File

@ -83,12 +83,20 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
##### SD Card I/O ##### ##### SD Card I/O #####
# create the generated SPICLK # create the generated SPICLK
#create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK] create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/spi.spi/SPICLK]
set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCS}] set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}]
set_input_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCIn}] set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}]
set_output_delay -clock [get_clocks mmcm_clkout1] 0 [get_ports {SDCCmd}] set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCIn}]
set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK] set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCIn}]
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCD}]
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCD}]
set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}]
set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}]
set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}]
create_generated_clock -name SPISDCClockOut -multiply_by 1 -source [get_pins sdcclkoddr/C] [get_ports SDCCLK]
set_clock_latency -source -max 3.0 [get_ports SDCCLK]
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]

131
fpga/constraints/small-debug-spi.xdc Normal file
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@ -0,0 +1,131 @@
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
startgroup
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftIn} ]]
create_debug_port u_ila_0 probe
set_property port_width 8 [get_debug_ports u_ila_0/probe9]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[7]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SCLKenable} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SampleEdge} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/Active} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe13]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPIOut} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICS[0]} ]]
create_debug_port u_ila_0 probe
set_property port_width 12 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[8]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[9]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[10]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[11]} ]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckMode[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckMode[1]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftRegLoad} ]]
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
connect_debug_port dbg_hub/clk [get_nets CPUCLK]

32
fpga/generator/Makefile
View File

@ -7,22 +7,34 @@ all: ArtyA7
ArtyA7: export XILINX_PART := xc7a100tcsg324-1 ArtyA7: export XILINX_PART := xc7a100tcsg324-1
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
ArtyA7: export board := ArtyA7 ArtyA7: export board := ArtyA7
ArtyA7: export SYSTEMCLOCK := 20000000
ArtyA7: export MAXSDCCLOCK := 5000000
ArtyA7: FPGA_Arty ArtyA7: FPGA_Arty
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
vcu118: export board := vcu118 vcu118: export board := vcu118
vcu118: export SYSTEMCLOCK := 71000000
vcu118: export MAXSDCCLOCK := 1000000
vcu118: FPGA_VCU vcu118: FPGA_VCU
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7 vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
vcu108: export board := vcu108 vcu108: export board := vcu108
vcu108: export SYSTEMCLOCK := 50000000
vcu108: export MAXSDCCLOCK := 12500000
vcu108: FPGA_VCU vcu108: FPGA_VCU
# variables computed from config
EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
EXT_MEM_RANGE = $(shell grep 'EXT_MEM_RANGE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/\1/g' | sed 's/\(.*\)/base=16;\1+1/g' | bc | sed 's/\(.*\)/0x\1/g')
.PHONY: FPGA_Arty FPGA_VCU .PHONY: FPGA_Arty FPGA_VCU
FPGA_Arty: PreProcessFiles IP_Arty FPGA_Arty: PreProcessFiles IP_Arty zsbl
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
FPGA_VCU: PreProcessFiles IP_VCU FPGA_VCU: PreProcessFiles IP_VCU zsbl
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
# Generate IP Blocks # Generate IP Blocks
@ -33,13 +45,9 @@ IP_VCU: $(dst)/sysrst.log \
$(dst)/ahbaxibridge.log $(dst)/ahbaxibridge.log
IP_Arty: $(dst)/sysrst.log \ IP_Arty: $(dst)/sysrst.log \
MEM_Arty \ MEM_Arty \
$(dst)/xlnx_mmcm.log \ $(dst)/mmcm.log \
$(dst)/clkconverter.log \ $(dst)/clkconverter.log \
$(dst)/ahbaxibridge.log $(dst)/ahbaxibridge.log
#$(dst)/xlnx_axi_crossbar.log \
#$(dst)/xlnx_axi_dwidth_conv_32to64.log \
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \
#$(dst)/xlnx_axi_prtcl_conv.log
# Generate Memory IP Blocks # Generate Memory IP Blocks
.PHONY: MEM_VCU MEM_Arty .PHONY: MEM_VCU MEM_Arty
@ -57,15 +65,19 @@ PreProcessFiles:
cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
mkdir ../src/CopiedFiles_do_not_add_to_repo/config/ mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ cp ../../config/deriv/fpga$(board)/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
./insert_debug_comment.sh ./insert_debug_comment.sh
# modify config *** RT: eventually setup for variably defined sized memory
#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA # This line allows the Bootloader to be loaded in a Block RAM on the FPGA
sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
# build the Zero stage boot loader (ZSBL)
.PHONY: zsbl
zsbl:
$(MAKE) -C ../zsbl clean
SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl
# Generate Individual IP Blocks # Generate Individual IP Blocks
$(dst)/%.log: %.tcl $(dst)/%.log: %.tcl
mkdir -p IP mkdir -p IP

5
fpga/generator/ddr4-vcu108.tcl
View File

@ -1,11 +1,14 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4
set ipName ddr4 set ipName ddr4
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000]
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]
@ -38,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \ CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ $SYSTEMCLOCK_MHz \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

5
fpga/generator/ddr4-vcu118.tcl
View File

@ -1,11 +1,14 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4
set ipName ddr4 set ipName ddr4
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]
@ -38,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \ CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ $SYSTEMCLOCK_MHz \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

10
fpga/generator/mmcm.tcl
View File

@ -1,25 +1,29 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
set ipName mmcm set ipName mmcm
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.NUM_OUT_CLKS {3} \ CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKIN1_JITTER_PS {10.0} \ CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName] ] [get_ips $ipName]
#set_property CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]

7
fpga/src/fpgaTop.sv
View File

@ -182,6 +182,7 @@ module fpgaTop
logic [511 : 0] dbg_bus; logic [511 : 0] dbg_bus;
logic CLK208; logic CLK208;
logic SDCCLKInternal;
assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
assign GPO = GPIOOUT[4:0]; assign GPO = GPIOOUT[4:0];
@ -215,7 +216,11 @@ module fpgaTop
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
.GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK(SDCCLKInternal), .ExternalStall(RVVIStall));
// *** these are different for different fpga ugh.
ODDRE1 sdcclkoddr(.Q(SDCCLK), .C(SDCCLKInternal), .D1('0),
.D2(1'b1), .SR('0));
// ahb lite to axi bridge // ahb lite to axi bridge
ahbaxibridge ahbaxibridge ahbaxibridge ahbaxibridge

8
fpga/zsbl/Makefile
View File

@ -27,11 +27,17 @@ MABI :=-mabi=lp64d
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
LINKER :=linker1000.x LINKER :=linker1000.x
# FGPA parameters
SYSTEMCLOCK ?= 20000000
MAXSDCCLOCK ?= 5000000
EXT_MEM_BASE ?= 0x80000000
EXT_MEM_RANGE ?= 0x10000000
AFLAGS =$(MARCH) $(MABI) -W AFLAGS =$(MARCH) $(MABI) -W
# Override directive allows us to prepend other options on the command line # Override directive allows us to prepend other options on the command line
# e.g. $ make CFLAGS=-g # e.g. $ make CFLAGS=-g
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -DSYSTEMCLOCK=${SYSTEMCLOCK} -DMAXSDCCLOCK=${MAXSDCCLOCK} -DEXT_MEM_BASE=${EXT_MEM_BASE} -DEXT_MEM_RANGE=${EXT_MEM_RANGE}
AS=riscv64-unknown-elf-as AS=riscv64-unknown-elf-as
CC=riscv64-unknown-elf-gcc CC=riscv64-unknown-elf-gcc
AR=riscv64-unknown-elf-ar AR=riscv64-unknown-elf-ar

13
fpga/zsbl/bios.s → fpga/zsbl/bios.S
View File

@ -1,5 +1,6 @@
PERIOD = 11000000 #include "system.h"
#PERIOD = 20
PERIOD = (SYSTEMCLOCK / 2)
.section .init .section .init
.global _start .global _start
@ -47,10 +48,10 @@ _start:
# set the stack pointer to the top of memory - 8 bytes (pointer size) # set the stack pointer to the top of memory - 8 bytes (pointer size)
li sp, 0x87FFFFF8 li sp, (EXT_MEM_END - 8)
li a0, 0x00000000 li a0, 0x00000000
li a1, 0x80000000 li a1, EXT_MEM_BASE
#li a2, 128*1024*1024/512 # copy 128MB #li a2, 128*1024*1024/512 # copy 128MB
li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra)
#li a2, 800 # copy 400KB #li a2, 800 # copy 400KB
@ -88,9 +89,9 @@ delay2:
jumpToLinux: jumpToLinux:
csrrs a0, 0xF14, x0 # copy hart ID to a0 csrrs a0, 0xF14, x0 # copy hart ID to a0
li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB li a1, FDT_ADDRESS # This is the device tree address
la a2, end_of_bios la a2, end_of_bios
li t0, 0x80000000 # start of code li t0, EXT_MEM_BASE # start of code
jalr x0, t0, 0 jalr x0, t0, 0

13
fpga/zsbl/boot.h
View File

@ -31,6 +31,7 @@
#define WALLYBOOT 10000 #define WALLYBOOT 10000
#include <stdint.h> #include <stdint.h>
#include "system.h"
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */ typedef unsigned char BYTE; /* char must be 8-bit */
typedef uint16_t WORD; /* 16-bit unsigned integer */ typedef uint16_t WORD; /* 16-bit unsigned integer */
@ -44,8 +45,10 @@ typedef QWORD LBA_t;
// These locations are copied from the generic configuration // These locations are copied from the generic configuration
// of OpenSBI. These addresses can be found in: // of OpenSBI. These addresses can be found in:
// buildroot/output/build/opensbi-0.9/platform/generic/config.mk // buildroot/output/build/opensbi-0.9/platform/generic/config.mk
#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR
#define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START // FDT_ADDRESS now defined in system.h
//#define FDT_ADDRESS 0xFF000000 // FW_JUMP_FDT_ADDR
#define OPENSBI_ADDRESS EXT_MEM_BASE // FW_TEXT_START
#define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR #define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR
#define BANNER " █▀█ █▀█ █▀█ █▀▀ █ █\r\n" \ #define BANNER " █▀█ █▀█ █▀█ █▀▀ █ █\r\n" \
@ -61,12 +64,6 @@ typedef QWORD LBA_t;
// Export disk_read // Export disk_read
int disk_read(BYTE * buf, LBA_t sector, UINT count); int disk_read(BYTE * buf, LBA_t sector, UINT count);
#define SYSTEMCLOCK 20000000
// TODO: This line needs to change back to 20MHz when we fix the
// timing problems.
#define MAXSDCCLOCK 5000000
// Maximum SDC speed is either the system clock divided by 2 (because // Maximum SDC speed is either the system clock divided by 2 (because
// of the SPI peripheral clock division) or the maximum speed an SD // of the SPI peripheral clock division) or the maximum speed an SD
// card can be pushed to. // card can be pushed to.

23
fpga/zsbl/system.h Normal file
View File

@ -0,0 +1,23 @@
#ifndef __system_H
#define __system_H
#ifndef SYSTEMCLOCK
#define SYSTEMCLOCK 100000000
#endif
#ifndef MAXSDCCLOCK
#define MAXSDCCLOCK 5000000
#endif
#ifndef EXT_MEM_BASE
#define EXT_MEM_BASE 0x80000000
#endif
#ifndef EXT_MEM_RANGE
#define EXT_MEM_RANGE 0x10000000
#endif
#define EXT_MEM_END (EXT_MEM_BASE + EXT_MEM_RANGE)
#define FDT_ADDRESS (EXT_MEM_END - 0x1000000)
#endif

2
linux/devicetree/wally-vcu108.dts
View File

@ -15,7 +15,7 @@
memory@80000000 { memory@80000000 {
device_type = "memory"; device_type = "memory";
reg = <0x00 0x80000000 0x00 0x10000000>; reg = <0x00 0x80000000 0x00 0x80000000>;
}; };
cpus { cpus {

10
src/uncore/spi_apb.sv
View File

@ -90,6 +90,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark; logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty; logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
logic TransmitFIFOWriteIncrement; logic TransmitFIFOWriteIncrement;
logic ReceiveFiFoWriteInc;
logic ReceiveFIFOReadIncrement; logic ReceiveFIFOReadIncrement;
logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty; logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
logic [7:0] TransmitFIFOReadData; logic [7:0] TransmitFIFOReadData;
@ -301,7 +302,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// Tx/Rx FIFOs // Tx/Rx FIFOs
spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0], spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark); TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveFiFoWriteInc, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark); ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
@ -311,6 +312,13 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (~PRESETn) ReceiveShiftFullDelay <= 1'b0; if (~PRESETn) ReceiveShiftFullDelay <= 1'b0;
else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull; else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
assign ReceiveFiFoTakingData = ReceiveFiFoWriteInc & ~ReceiveFIFOWriteFull;
always_ff @(posedge PCLK)
if (~PRESETn) ReceiveFiFoWriteInc <= 1'b0;
else if (SCLKenable & ReceiveShiftFull) ReceiveFiFoWriteInc <= 1'b1;
else if (SCLKenable & ReceiveFiFoTakingData) ReceiveFiFoWriteInc <= 1'b0;
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0; if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0;
else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull; else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull;