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https://github.com/openhwgroup/cvw
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busybear: quick fix to mem reading
also stop ignoring mcause at the start
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@ -191,7 +191,7 @@ module testbench_busybear();
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logic [`XLEN-1:0] readAdrExpected;
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logic [`XLEN-1:0] readAdrExpected;
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always @(dut.HRDATA) begin
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always @(dut.HRDATA) begin
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#1;
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#2;
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if (dut.hart.MemRWM[1] && HADDR[31:3] != dut.PCF[31:3] && dut.HRDATA !== {64{1'bx}}) begin
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if (dut.hart.MemRWM[1] && HADDR[31:3] != dut.PCF[31:3] && dut.HRDATA !== {64{1'bx}}) begin
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//$display("%0t", $time);
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//$display("%0t", $time);
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if($feof(data_file_memR)) begin
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if($feof(data_file_memR)) begin
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@ -282,16 +282,14 @@ module testbench_busybear();
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//CSR checking \
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//CSR checking \
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always @(``PATH``.``CSR``_REGW) begin \
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always @(``PATH``.``CSR``_REGW) begin \
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if ($time > 1) begin \
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if ($time > 1) begin \
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if (instrs > 1) begin \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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if(CSR.icompare(`"CSR`")) begin \
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if(CSR.icompare(`"CSR`")) begin \
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$display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
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$display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
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end \
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end \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
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$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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`ERROR \
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`ERROR \
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end \
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end \
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end \
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end else begin \
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end else begin \
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for(integer j=0; j<totalCSR; j++) begin \
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for(integer j=0; j<totalCSR; j++) begin \
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