From 2db536bf49cb3aff29c26f4d54d01b9f4cf6526a Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Thu, 6 Feb 2025 23:47:43 -0800
Subject: [PATCH 1/2] Adding RISC-V Assertions

---
 testbench/testbench.sv | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 696a288f1..818232287 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -28,6 +28,7 @@
 `include "config.vh"
 `include "tests.vh"
 `include "BranchPredictorType.vh"
+// `include "RV32VM_coverage copy.sv"
 
 `ifdef USE_IMPERAS_DV
     `include "idv/idv.svh"
@@ -292,7 +293,8 @@ module testbench;
     # 100;
     TestBenchReset = 1'b0;
   end
-
+   mcount u_mcounteren_checker (
+    );
   always_ff @(posedge clk)
     if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
     else CurrState <= NextState;
@@ -751,6 +753,8 @@ end
               .CMP_CSR     (1)
               ) idv_trace2api(rvvi);
 
+  `include "RV_Assertions.sv"
+
   string filename;
   initial begin
     // imperasDV requires the elffile be defined at the begining of the simulation.

From ed7b616c5b1a73e25e5fe21a6f6fe14bd4d69331 Mon Sep 17 00:00:00 2001
From: Huda-10xe <huda.sajjad@10xengineers.ai>
Date: Fri, 7 Feb 2025 00:13:27 -0800
Subject: [PATCH 2/2] Removing excess code

---
 testbench/testbench.sv | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 818232287..4749b26ab 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -28,7 +28,6 @@
 `include "config.vh"
 `include "tests.vh"
 `include "BranchPredictorType.vh"
-// `include "RV32VM_coverage copy.sv"
 
 `ifdef USE_IMPERAS_DV
     `include "idv/idv.svh"
@@ -293,8 +292,7 @@ module testbench;
     # 100;
     TestBenchReset = 1'b0;
   end
-   mcount u_mcounteren_checker (
-    );
+
   always_ff @(posedge clk)
     if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
     else CurrState <= NextState;