From 1b18568d870dac9d2b764adaf00861cca3561b3c Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Wed, 17 Apr 2024 09:39:21 -0700 Subject: [PATCH 1/2] the fix Rose provided in meeting --- testbench/testbench-imperas.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv index 27bcdb73e..49f321d00 100644 --- a/testbench/testbench-imperas.sv +++ b/testbench/testbench-imperas.sv @@ -110,7 +110,7 @@ module testbench; $error("Must specify test directory using plusarg testDir"); end - if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM); else $error("Imperas test bench requires BUS."); ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"}; From 6f16b7e0c9e55122a4787bbcb70bbec266457515 Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Wed, 17 Apr 2024 10:25:36 -0700 Subject: [PATCH 2/2] updated the submodules -> riscv-arch-tests and riscv-dv --- addins/riscv-arch-test | 2 +- addins/riscv-dv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a0cdceca..59ae6e707 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b +Subproject commit 59ae6e7073ff40c7e1a1556547b2e8b2ba03ea04 diff --git a/addins/riscv-dv b/addins/riscv-dv index a7e27bc04..f0c570d11 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 +Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580