From 9e2a2ec31b517504321a9358f673277da5c41241 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 9 Feb 2025 12:36:41 -0800 Subject: [PATCH] Make disassemble a function instead of a module --- testbench/common/trace2riscvISACOV.sv | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/testbench/common/trace2riscvISACOV.sv b/testbench/common/trace2riscvISACOV.sv index d45bf70fb..307d0e8d5 100644 --- a/testbench/common/trace2riscvISACOV.sv +++ b/testbench/common/trace2riscvISACOV.sv @@ -1,9 +1,15 @@ // trace2riscvISACOV.sv // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Load which extensions are supported in this configuration (from $WALLY/config//coverage.svh) +`include "coverage.svh" +`include "disassemble.svh" + +// Load the coverage classes `include "RISCV_coverage.svh" module trace2riscvISACOV(rvviTrace rvvi); + string disass; // Connect coverage class to RVVI trace interface coverage #(rvvi.ILEN, rvvi.XLEN, rvvi.FLEN, rvvi.VLEN, rvvi.NHART, rvvi.RETIRE) riscvISACOV; initial begin @@ -11,17 +17,15 @@ module trace2riscvISACOV(rvviTrace rvvi); $display("trace2riscvISACOV: coverage initialized"); end - // Dissassemble instruction from RVVI trace for processing by coverage model - string disass; - dissassembler #(rvvi.XLEN) dissassembler(rvvi.insn[0][0], disass); - // Invoke the riscvISACOV sample function on each clock edge for the current Instruction // If RVVI accepts more than one instruction or hart, iterate over all of them in the // correct order of retirement (TODO: multiple instructions/harts not implemented) always_ff @(posedge rvvi.clk) begin if (rvvi.valid[0][0] == 1) begin + disass = disassemble(rvvi.insn[0][0]); riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass}); - $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + // $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + $display("0x%h: %s", rvvi.insn[0][0], disass); end end endmodule