From 9e1f03f93b9a69f94ccaf364c025724859cc89b2 Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Mon, 12 Jun 2023 20:49:46 -0700
Subject: [PATCH] Update ahbapbbridge.sv

Program clean up
---
 src/uncore/ahbapbbridge.sv | 33 ++++++++++++++++-----------------
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
index 5aed30300..381297f00 100644
--- a/src/uncore/ahbapbbridge.sv
+++ b/src/uncore/ahbapbbridge.sv
@@ -27,27 +27,27 @@
 
 module ahbapbbridge import cvw::*;  #(parameter cvw_t P, 
                                       parameter PERIPHS = 2) (
-  input  logic                HCLK, HRESETn,
-  input  logic [PERIPHS-1:0]  HSEL,  
+  input  logic                 HCLK, HRESETn,
+  input  logic [PERIPHS-1:0]   HSEL,  
   input  logic [P.PA_BITS-1:0] HADDR, 
   input  logic [P.XLEN-1:0]    HWDATA,
   input  logic [P.XLEN/8-1:0]  HWSTRB,
-  input  logic                HWRITE,
-  input  logic [1:0]          HTRANS,
-  input  logic                HREADY,
+  input  logic                 HWRITE,
+  input  logic [1:0]           HTRANS,
+  input  logic                 HREADY,
 //  input  logic [3:0]        HPROT, // not used
   output logic [P.XLEN-1:0]    HRDATA,
-  output logic                HRESP, HREADYOUT,
-  output logic                PCLK, PRESETn,
-  output logic [PERIPHS-1:0]  PSEL,
-  output logic                PWRITE,
-  output logic                PENABLE,
-  output logic [31:0]         PADDR,
+  output logic                 HRESP, HREADYOUT,
+  output logic                 PCLK, PRESETn,
+  output logic [PERIPHS-1:0]   PSEL,
+  output logic                 PWRITE,
+  output logic                 PENABLE,
+  output logic [31:0]          PADDR,
   output logic [P.XLEN-1:0]    PWDATA,
 //  output logic [2:0]        PPROT, // not used
   output logic [P.XLEN/8-1:0]  PSTRB,
 //  output logic              PWAKEUP // not used
-  input  logic [PERIPHS-1:0]  PREADY,
+  input  logic [PERIPHS-1:0]   PREADY,
   input  var   [PERIPHS-1:0][P.XLEN-1:0] PRDATA
 );
 
@@ -56,15 +56,15 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
   logic                       PREADYOUT;
 
   // convert AHB to APB signals
-  assign PCLK = HCLK;
+  assign PCLK    = HCLK;
   assign PRESETn = HRESETn;
 
   // identify start of a transaction
-  assign initTrans = HTRANS[1] & HREADY;  // start a transaction when the bus is ready and an active transaction is requested
+  assign initTrans    = HTRANS[1] & HREADY;  // start a transaction when the bus is ready and an active transaction is requested
   assign initTransSel = initTrans & |HSEL; // capture data and address if any of the peripherals are selected
 
   // delay AHB Address phase signals to align with AHB Data phase because APB expects them at the same time
-  flopen #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
+  flopen  #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
   flopenr #(1) writereg(HCLK, ~HRESETn, HREADY, HWRITE, PWRITE); 
   flopenr #(PERIPHS) selreg(HCLK, ~HRESETn, HREADY, HSEL & {PERIPHS{initTrans}}, PSEL); 
   // PPROT[2:0] = {Data/InstrB, Secure, Privileged};
@@ -73,7 +73,7 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
 
   // AHB Data phase signal doesn't need delay.  Note that they are guaranteed to remain stable until READY is asserted
   assign PWDATA = HWDATA;
-  assign PSTRB = HWSTRB;
+  assign PSTRB  = HWSTRB;
 
   // enable logic: goes high a cycle after initTrans, then back low on cycle after desired PREADY is asserted
   // cycle1: AHB puts HADDR, HWRITE, HSEL on bus.  initTrans is 1, and these are captured
@@ -103,4 +103,3 @@ assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before a
   // resp logic
   assign HRESP = 0; // bridge never indicates errors
 endmodule
-