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https://github.com/openhwgroup/cvw
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More signal renames.
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@ -45,7 +45,7 @@ module gshare #(parameter k = 10,
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logic MatchF, MatchD, MatchE, MatchM, MatchW;
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logic MatchX;
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logic [1:0] TableBPDirPredF, BPDirPredD, BPDirPredE, ForwardNewBPDirPredF;
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logic [1:0] TableBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF;
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logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
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logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
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@ -76,12 +76,12 @@ module gshare #(parameter k = 10,
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assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
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assign MatchX = MatchD | MatchE | MatchM | MatchW;
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assign ForwardNewBPDirPredF = MatchD ? {2{BPDirPredD[1]}} :
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assign FwdNewDirPredF = MatchD ? {2{BPDirPredD[1]}} :
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MatchE ? {NewBPDirPredE} :
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MatchM ? {NewBPDirPredM} :
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NewBPDirPredW ;
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assign BPDirPredF = MatchX ? ForwardNewBPDirPredF : TableBPDirPredF;
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assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF;
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(~StallM & ~FlushM),
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