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Updated coremark testbench with the extra ports from FPGA merge.

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Fixed coremark Makefile to create work directory.
This commit is contained in:
Ross Thompson 2021-12-08 13:40:32 -06:00
parent 4dbd5d45ee
commit 9ddd065340
3 changed files with 13 additions and 7 deletions
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7
benchmarks/riscv-coremark/Makefile
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@ -14,10 +14,11 @@ work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
work/coremark.bare.riscv: $(sources) work/coremark.bare.riscv: $(sources)
# make -C $(cmbase) PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64g" # make -C $(cmbase) PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64g"
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im" make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv XCFLAGS="-march=rv64imd"
mv $(cmbase)/coremark.bare.riscv work mkdir -p work/
mv $(cmbase)/coremark.bare.riscv work/
.PHONY: clean .PHONY: clean
clean: clean:
rm -f work/* rm -f work/*

2
wally-pipelined/regression/wally-coremark.do
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@ -35,7 +35,7 @@ vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testb
vopt +acc work.testbench -o workopt vopt +acc work.testbench -o workopt
vsim workopt vsim workopt
mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/dtim/RAM
view wave view wave

11
wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -54,8 +54,13 @@ module testbench();
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
logic UARTSin, UARTSout; logic UARTSin, UARTSout;
logic SDCCLK; logic SDCCLK;
tri1 SDCCmd; logic SDCCmdIn;
tri1 [3:0] SDCDat; logic SDCCmdOut;
logic SDCCmdOE;
logic [3:0] SDCDatIn;
logic HREADY;
logic HSELEXT;
assign SDCmd = 1'bz; assign SDCmd = 1'bz;
assign SDCDat = 4'bz; assign SDCDat = 4'bz;
@ -95,7 +100,7 @@ module testbench();
totalerrors = 0; totalerrors = 0;
// read test vectors into memory // read test vectors into memory
memfilename = tests[0]; memfilename = tests[0];
$readmemh(memfilename, dut.uncore.dtim.RAM); $readmemh(memfilename, dut.uncore.dtim.dtim.RAM);
//for(j=268437955; j < 268566528; j = j+1) //for(j=268437955; j < 268566528; j = j+1)
//dut.uncore.dtim.RAM[j] = 64'b0; //dut.uncore.dtim.RAM[j] = 64'b0;
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";