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This icpred and btb changes are causing a performance issue.

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Ross Thompson 2023-02-27 20:00:50 -06:00
parent 544abe2819
commit 9dd3379744
1 changed files with 2 additions and 2 deletions
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src/ifu/bpred/bpred.sv
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@ -174,9 +174,9 @@ module bpred (
// this will result in PCD not being equal to the fall through address PCLinkE (PCE+4). // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
// The next instruction is always valid as no other flush would occur at the same time as the branch and not // The next instruction is always valid as no other flush would occur at the same time as the branch and not
// also flush the branch. This will change in a superscaler cpu. // also flush the branch. This will change in a superscaler cpu.
assign BPPCWrongE = PCCorrectE != PCD; assign BPPCWrongE = ;
// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
assign BPWrongE = BPPCWrongE & InstrValidE & InstrValidD; assign BPWrongE = (PCCorrectE != PCD) & InstrValidE & InstrValidD;
flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM);
// Output the predicted PC or corrected PC on miss-predict. // Output the predicted PC or corrected PC on miss-predict.