diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index ee8359263..af2a7ace4 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -907,15 +907,15 @@ string imperas32f[] = '{ string wally64a[] = '{ `WALLYTEST, - "rv64i_m/privilege/src/WALLY-amo.S", - "rv64i_m/privilege/src/WALLY-lrsc.S", + "rv64i_m/privilege/src/WALLY-amo-01.S", + "rv64i_m/privilege/src/WALLY-lrsc-01.S", "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S" }; string wally32a[] = '{ `WALLYTEST, - "rv32i_m/privilege/src/WALLY-amo.S", - "rv32i_m/privilege/src/WALLY-lrsc.S", + "rv32i_m/privilege/src/WALLY-amo-01.S", + "rv32i_m/privilege/src/WALLY-lrsc-01.S", "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S" }; @@ -1804,11 +1804,11 @@ string imperas32f[] = '{ "rv64i_m/privilege/src/WALLY-mie-01.S", "rv64i_m/privilege/src/WALLY-minfo-01.S", "rv64i_m/privilege/src/WALLY-misa-01.S", - "rv64i_m/privilege/src/WALLY-mmu-sv39.S", - "rv64i_m/privilege/src/WALLY-mmu-sv48.S", + "rv64i_m/privilege/src/WALLY-mmu-sv39-01.S", + "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S", "rv64i_m/privilege/src/WALLY-mtvec-01.S", - "rv64i_m/privilege/src/WALLY-pma.S", - "rv64i_m/privilege/src/WALLY-pmp.S", + "rv64i_m/privilege/src/WALLY-pma-01.S", + "rv64i_m/privilege/src/WALLY-pmp-01.S", "rv64i_m/privilege/src/WALLY-sie-01.S", "rv64i_m/privilege/src/WALLY-status-mie-01.S", "rv64i_m/privilege/src/WALLY-status-sie-01.S", @@ -1826,7 +1826,12 @@ string imperas32f[] = '{ string wally64periph[] = '{ `WALLYTEST, - "rv64i_m/privilege/src/WALLY-periph.S" + "rv64i_m/privilege/src/WALLY-periph-01.S", + "rv64i_m/privilege/src/WALLY-clint-01.S", + "rv64i_m/privilege/src/WALLY-gpio-01.S", + "rv64i_m/privilege/src/WALLY-plic-01.S", + "rv64i_m/privilege/src/WALLY-plic-s-01.S", + "rv64i_m/privilege/src/WALLY-uart-01.S" }; string wally32e[] = '{ @@ -1886,10 +1891,10 @@ string imperas32f[] = '{ "rv32i_m/privilege/src/WALLY-mie-01.S", "rv32i_m/privilege/src/WALLY-minfo-01.S", "rv32i_m/privilege/src/WALLY-misa-01.S", - "rv32i_m/privilege/src/WALLY-mmu-sv32.S", + "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S", "rv32i_m/privilege/src/WALLY-mtvec-01.S", - "rv32i_m/privilege/src/WALLY-pma.S", - "rv32i_m/privilege/src/WALLY-pmp.S", + "rv32i_m/privilege/src/WALLY-pma-01.S", + "rv32i_m/privilege/src/WALLY-pmp-01.S", "rv32i_m/privilege/src/WALLY-sie-01.S", "rv32i_m/privilege/src/WALLY-status-mie-01.S", "rv32i_m/privilege/src/WALLY-status-sie-01.S", @@ -1900,11 +1905,13 @@ string imperas32f[] = '{ "rv32i_m/privilege/src/WALLY-trap-sret-01.S", "rv32i_m/privilege/src/WALLY-trap-u-01.S", "rv32i_m/privilege/src/WALLY-wfi-01.S", - "rv32i_m/privilege/src/WALLY-endianness-01.S" + "rv32i_m/privilege/src/WALLY-endianness-01.S", + "rv32i_m/privilege/src/WALLY-satp-invalid-01.S" }; string wally32periph[] = '{ `WALLYTEST, + //"rv32i_m/privilege/src/WALLY-periph-01.S", "rv32i_m/privilege/src/WALLY-gpio-01.S", "rv32i_m/privilege/src/WALLY-clint-01.S", "rv32i_m/privilege/src/WALLY-uart-01.S", @@ -1915,7 +1922,7 @@ string imperas32f[] = '{ string wally32d[] = '{ `WALLYTEST, - "rv32i_m/D/src/WALLY-fld.S" + "rv32i_m/D/src/WALLY-fld-01.S" }; string fpga[] = '{ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output new file mode 100644 index 000000000..25745a989 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output @@ -0,0 +1,496 @@ +01BEEF00 +8000000B +00000000 +0000000A +00000004 +00000061 +00000061 +00000068 +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01BEEF01 +8000000B +00000000 +00000003 +00080000 +00080000 +00080000 +00000000 +00000000 +00000000 +00080000 +00080000 +FFFFFFFF +FFF7FFFF +00000000 +00000000 +01BEEF02 +8000000B +00000000 +00000003 +00000001 +00000001 +00000001 +00000000 +00080000 +00000000 +00080001 +00000001 +FFFFFFFF +FFFFFFFE +00000000 +00000000 +01BEEF03 +8000000B +00000000 +0000000A +00000004 +00000061 +00000061 +00000065 +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +02BEEF04 +8000000B +00000000 +00000003 +0000F0F0 +3030F0F0 +0000F0F0 +00000000 +00000001 +00000000 +0000F0F1 +0000F0F0 +FFFFFFFF +FFFF0F0F +00000000 +00000000 +02BEEF05 +8000000B +00000000 +00000003 +30300000 +3030F0F0 +30300000 +00000000 +0000F0F0 +00000000 +3030F0F0 +30300000 +FFFFFFFF +CFCFFFFF +00000000 +00000000 +02BEEF06 +8000000B +00000000 +00000003 +30000000 +3030F0F0 +00000000 +00000000 +00300000 +00000000 +30300000 +30000000 +CFFFFFFF +CFFFFFFF +00000000 +00000000 +02BEEF07 +8000000B +00000000 +00000003 +0F000000 +0F0F0F0F +0F000000 +00000000 +30000000 +00000000 +3F000000 +0F000000 +FFFFFFFF +F0FFFFFF +00000000 +00000000 +02BEEF08 +8000000B +00000000 +00000003 +00FFFF00 +00FFFF00 +00FFFF00 +00000000 +00000000 +00000000 +00FFFF00 +00FFFF00 +FFFFFFFF +FF0000FF +00000000 +00000000 +02BEEF09 +8000000B +00000000 +00000003 +33FFFF33 +33FFFF33 +33000033 +00000000 +00000000 +00000000 +33FFFF33 +33FFFF33 +FF0000FF +CC0000CC +00000000 +00000000 +02BEEF0A +8000000B +00000000 +00000003 +33000033 +33000033 +00000000 +00000000 +00FFFF00 +00000000 +33FFFF33 +33000033 +CCFFFFCC +CCFFFFCC +00000000 +00000000 +02BEEF0B +8000000B +00000000 +00000003 +00CCCC00 +00CCCC00 +00CCCC00 +00000000 +33000033 +00000000 +33CCCC33 +00CCCC00 +FFFFFFFF +FF3333FF +00000000 +00000000 +02BEEF0C +8000000B +00000000 +00000003 +00CCCC00 +00CCCC00 +00000000 +00000000 +00000000 +00000000 +00CCCC00 +00CCCC00 +FF3333FF +FF3333FF +00000000 +00000000 +02BEEF0D +8000000B +00000000 +00000003 +CC00CCCC +CCCCCCCC +CC00CCCC +00000000 +00CCCC00 +00000000 +CC00CCCC +CC00CCCC +FFFFFFFF +33FF3333 +00000000 +00000000 +02BEEF0E +8000000B +00000000 +00000003 +CCCCCCCC +CCCCCCCC +00CC0000 +00000000 +00000000 +00000000 +CCCCCCCC +CCCCCCCC +33FF3333 +33333333 +00000000 +00000000 +02BEEF0F +8000000B +00000000 +00000003 +000011FF +FF1111FF +33333333 +00000000 +FFFFEE00 +00000000 +FFFFFFFF +000011FF +FFFFEE00 +FFFFEE00 +00000000 +00000000 +02BEEF10 # Something here is failing +8000000B +00000000 +00000003 +000000FF +00000000 +000000FF +00000000 +00000000 +00000000 +000000FF +000000FF +FFFFFFFF +FFFFFF00 +00000000 +00000000 +02BEEF11 # this might be wrong +8000000B +00000000 +00000003 +00000033 # input +00000000 # output +00000000 # rise ip +00000000 # serviced rise ip +000000CC # fall ip +00000000 +000000FF # high ip +00000033 # why is this 0x33? +FFFFFFCC # low ip +FFFFFFCC # serviced low ip +00000000 +00000000 +03BEEF12 +8000000B +00000000 +0000000A +00000002 +00000061 +00000061 +0000006C +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF13 +8000000B +00000000 +0000000A +00000002 +00000021 +00000021 +0000006C +00000020 +00000001 +00000002 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF14 +8000000B +00000000 +0000000A +00000004 +00000061 +00000061 +0000006F +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF15 +8000000B +00000000 +0000000A +00000004 +00000061 +00000061 +00000020 +00000060 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF16 +8000000B +00000000 +0000000A +00000004 +00000061 +00000061 +00000074 +00000060 +00000001 +00000020 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF17 +8000000B +00000000 +0000000A +00000002 +00000020 +00000020 +00000074 +00000020 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF18 +8000000B +00000000 +0000000A +00000002 +00000020 +00000020 +00000074 +00000020 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF19 +8000000B +00000000 +0000000A +00000004 +00000061 +00000061 +00000065 +00000060 +00000001 +00000003 +00000000 +00000000 +00000000 +00000000 +00000000 +03BEEF1A +8000000B +00000000 +0000000A +00000006 +00000063 +00000061 +00000047 +00000060 +00000001 +000000FF +00000000 +00000000 +00000000 +00000000 +00000000 +04BEEF1B +80000009 +00000000 +0000000A +00000004 +00000061 +00000061 +00000065 +00000060 +00000001 +000000ff +00000000 +00000000 +00000000 +00000000 +00000000 +04BEEF1C +80000009 +00000000 +00000003 +00080000 +00080000 +00080000 +00000000 +00000000 # is it this one that's failing? +00000000 +00080000 # failing +00080000 +FFFFFFFF +FFF7FFFF +00000000 +00000000 +04BEEF1D +80000009 +00000000 +00000003 +00000001 +00000001 +00000001 +00000000 +00080000 +00000000 +00080001 +00000001 +FFFFFFFF +FFFFFFFE +00000000 +00000000 +04BEEF1E # this might also be wrong +80000009 +00000000 +0000000A +00000004 +00000061 +00000061 +0000006e +00000060 +00000001 +000000ff +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output new file mode 100644 index 000000000..f0468cead --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output @@ -0,0 +1,3 @@ +0000000b # Test *** Number: Ecall from going from M mode to S mode +00000002 # illegal instruction from truining on virtual memory with invalid satp address +00000009 # ecall from ending tests in S mode. \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S new file mode 100644 index 000000000..46e2483d5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S @@ -0,0 +1,920 @@ +/////////////////////////////////////////// +// WALLY-PERIPH.S +// 64 bit version +// +// Ben Bracker (bbracker@hmc.edu) +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV32I") +// this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph) + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + j main_code +# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary +.align 2 +################### +################### +trap_handler: ##### +################### +################### + # save registers + addi sp, sp, 0x28 + sw t0, 0x00(sp) + sw t1, 0x08(sp) + sw t2, 0x10(sp) + sw t3, 0x18(sp) + sw t4, 0x20(sp) + + # =================================== + # ===== Signature Output Format ===== + # =================================== + # + # Base address = +0x40* + # Use sigout-translator.py for help with this! + # + # : + # 0x00: test ID = 0xBEEF + # 0x04: mcause (low) = 0x8000000B (MEIP) or 0x80000009 (SEIP) + # 0x08: mcause (high) = 0x00000000 + # ----- If GPIO ----- + # 0x0C: claim ID = 3 + # 0x10: input_val + # 0x14: output_val + # 0x18: incoming rise_ip + # 0x1C: serviced rise_ip = 0 + # 0x20: incoming fall_ip + # 0x24: serviced fall_ip = 0 + # 0x28: incoming high_ip + # 0x2C: serviced high_ip = 0 + # 0x30: incoming low_ip + # 0x34: serviced low_ip = 0 + # ----- If UART ----- + # 0x0C: claim ID = 0xA + # 0x10: IIR + # 0x14: LSR + # 0x18: LSR (after reading LSR) + # 0x1C: RBR + # 0x20: LSR (after reading RBR too) + # 0x24: IIR (after reading everything else) + # 0x28: SCR + + # 0x00: test ID = 0xBEEF + la t0, wally_signature + sub t0, s0, t0 # sigout offset + srli t0, t0, 6 # intr_num + add t0, t0, a1 + sw t0, 0x00(s0) + + # 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP) + # 0x08: mcause (high) = 0x80000000 + csrrc t0, mcause, x0 + andi t1, t0, 0x7FF + sw t0, 0x04(s0) + //srli t0,t0,32 + sw x0, 0x08(s0) + # MEIP or SEIP? + # MEIP is on context 0 + li t4, 0x0C200004 + li t0, 0xB + beq t1, t0, meip + # SEIP is on context 1 + li t4, 0x0C201004 + meip: + + # 0x0C: claim ID + # 3: GPIO + # A: UART + mv t0, t4 + lw t1, 0(t0) + sw t1, 0x0C(s0) + li t2, 0xA + beq t1, t2, uart_handler + li t2, 3 + bne t1, t2, trap_handler_end + + gpio_handler: + # 0x10: input_val + li t0, 0x10060000 + lw t1, 0x00(t0) + sw t1, 0x10(s0) + # 0x14: output_val + lw t1, 0x0C(t0) + sw t1, 0x14(s0) + # 0x18: incoming rise_ip + lw t1, 0x1C(t0) + sw t1, 0x18(s0) + # 0x1C: serviced rise_ip = 0 + sw t1, 0x1C(t0) + lw t1, 0x1C(t0) + sw t1, 0x1C(s0) + # 0x20: incoming fall_ip + lw t1, 0x24(t0) + sw t1, 0x20(s0) + # 0x24: serviced fall_ip = 0 + sw t1, 0x24(t0) + lw t1, 0x24(t0) + sw t1, 0x24(s0) + # 0x28: incoming high_ip + lw t1, 0x2C(t0) + sw t1, 0x28(s0) + # 0x2C: serviced high_ip = 0 + sw t1, 0x2C(t0) + lw t1, 0x2C(t0) + sw t1, 0x2C(s0) + # 0x30: incoming low_ip + lw t1, 0x34(t0) + sw t1, 0x30(s0) + # 0x34: serviced low_ip = 0 + sw t1, 0x34(t0) + lw t1, 0x34(t0) + sw t1, 0x34(s0) + # disable high_ie and low_ie so interrupt + # is not taken again immediately + li t1, 0 + sw t1, 0x28(t0) + sw t1, 0x30(t0) + # signal to main code that gpio was serviced + ori a0, a0, 0b00001000 + # signal to plic that gpio was serviced + mv t0, t4 + li t1, 3 + sw t1, 0(t0) + j trap_handler_end + + uart_handler: + # 0x10: IIR + li t0, 0x10000000 + lbu t1, 2(t0) + sw t1, 0x10(s0) + # 0x14: LSR + lbu t1, 5(t0) + sw t1, 0x14(s0) + # 0x18: LSR (after reading LSR) + lbu t1, 5(t0) + sw t1, 0x18(s0) + # 0x1C: RBR + lbu t1, 0(t0) + sw t1, 0x1C(s0) + # 0x20: LSR (after reading RBR) + lbu t1, 5(t0) + sw t1, 0x20(s0) + # 0x24: IIR (after reading everything else) + lbu t1, 2(t0) + sw t1, 0x24(s0) + # 0x28: SCR + lbu t1, 7(t0) + sw t1, 0x28(s0) + # signal to main code that uart was serviced + ori a0, a0, 0b00010000 + # signal to plic that uart was serviced + mv t0, t4 + li t1, 0xA + sw t1, 0(t0) + + trap_handler_end: + # increment signature pointer + addi s0,s0,0x40 + # restore vars + lw t0, 0x00(sp) + lw t1, 0x08(sp) + lw t2, 0x10(sp) + lw t3, 0x18(sp) + lw t4, 0x20(sp) + addi sp, sp, SEXT_IMM(-0x28) + mret + +################ +################ +main_code: ##### +################ +################ + + ########################## + ##### Initialization ##### + ########################## + # ========== Global Vars ========== + la s0, wally_signature # signature output base adr + la sp, stack # stack pointer + li a0, 0 # interrupt complete flag + # ========== Configure Privileged Unit ========== + # load address of trap handler + la t0, trap_handler + csrrw x0, mtvec, t0 + # delegate all external interrupts to machine mode + li t0, 0xD00 + csrrc x0, mideleg, t0 + # set MIE + li t0, 0x8 + csrrs x0, mstatus, t0 + + ################################## + ##### Test 1 - Signs of Life ##### + ################################## + li a1, 0x01beef00 # group ID + # clear MEIE (good to turn off while configuring peripherals) + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 3 (GPIO) priority = 6 + li t0, 0xC000000 + li t1, 6 + sw t1, 0x0C(t0) + # source 0xA (UART) priority = 7 + li t1, 7 + sw t1, 0x28(t0) + # enable sources 3,0xA + li t0, 0x0C002000 + li t1, 0b10000001000 + sw t1, 0(t0) + # ========== Configure UART ========== + # MCR: Loop = 1 + li t0, 0x10000000 + li t1, 0b10000 + sb t1, 4(t0) + # LCR: Use 8 data bits plus odd parity bit + li t1, 0b00001011 + sb t1, 3(t0) + # IER: Enable Received Data Available Interrupt + li t1, 0x01 + sb t1, 1(t0) + # ========== Configure GPIO ========== + # raise all input_en + li t0, 0x10060000 + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # raise all output_en + sw t1, 0x08(t0) + # raise all rise_en + sw t1, 0x18(t0) + # ========== Execute Test ========== + # set MEIE + li t0, 0x800 + csrrs x0, mie, t0 +Intr01BEEF00: + # UART TX 'h' + li t0, 0x10000000 + li t1, 'h' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr01BEEF01: + # GPIO raise pin 19 + li t0, 0x10060000 + li t1, 0x00080000 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # Now let's go bonkers and trigger both! +Intr01BEEF02: + # TX 'e' + li t0, 0x10000000 + li t1, 'e' + sb t1, 0(t0) +Intr01BEEF03: + # GPIO lower pin 19 raise pin 0 + li t0, 0x10060000 + li t1, 0x00000001 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00011000 + 1: bne t1,a0,1b + li a0, 0 + + ################################## + ##### Test 2 - GPIO Testing ##### + ################################## + li a1, 0x02beef00 # group ID + # clear MEIE + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 3 (GPIO) priority = 1 + li t0, 0xC000000 + li t1, 1 + sw t1, 0x0C(t0) + # enable source 3 + li t0, 0x0C002000 + li t1, 0b1000 + sw t1, 0(t0) + # ========== Input Enables ========== + # Note that this inherits + # a bit of state from the previous test. + # Namely output_val = 0x00000001 + # + # enable some inputs + li t0, 0x10060000 + li t1, 0x0000FFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # enable all rising edge interrupts + sw t1, 0x18(t0) + # set MEIE + li t1, 0x800 + csrrs x0, mie, t1 + # raise some input-disabled pins + # interrupt should not happen + li t1, 0xF0F00001 + sw t1, 0x0C(t0) +Intr02BEEF04: + # change some input-enabled pins + # interrupt should happen + li t1, 0x3030F0F0 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 +Intr02BEEF05: + # enable some different inputs + # this itself will cause some rise interrupts + li t1, 0xFFFF0000 + sw t1, 0x04(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Output Enables ========== + # enable all fall interrupts + li t1, 0xFFFFFFFF + sw t1, 0x20(t0) +Intr02BEEF06: + # disable some outputs + # should affect input value but not output val register itself + # this itself will cause some fall interrupts + li t1, 0xFF0000FF + sw t1, 0x08(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # change pins whose inputs and/or outputs are disabled + # should not cause any rise or fall interrupts + li t1, 0x300F0F0F + sw t1, 0x0C(t0) +Intr02BEEF07: + # change pins whose inputs and outputs are enabled + li t1, 0x0F0F0F0F + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Clear GPIO State ========== + # (I've gotten a little annoyed with tests depending + # upon the results of previous tests). + # disable all interrupts + sw x0, 0x18(t0) + sw x0, 0x20(t0) + sw x0, 0x28(t0) + sw x0, 0x30(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # set initial output state + sw x0, 0x0C(t0) + # clear all pending interrupts + li t1, 0xFFFFFFFF + sw t1, 0x1C(t0) + sw t1, 0x24(t0) + sw t1, 0x2C(t0) + sw t1, 0x34(t0) + # ========== Rise Interrupt Enables ========== + # enable some rising edge interrupts + li t1, 0x0000FFFF + sw t1, 0x18(t0) +Intr02BEEF08: + # raise some pins + li t1, 0x00FFFF00 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 +Intr02BEEF09: + # raise pins whose rise IEs are disabled + # should not cause an interrupt + li t1, 0x33FFFF00 + sw t1, 0x0C(t0) + # raise pins whose rise IEs are enabled + li t1, 0x33FFFF33 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # =========== Fall Interrupts =========== + # (admittedly these are already used elsewhere) + # disable all rising edge interrupts + li t1, 0 + sw t1, 0x18(t0) + # enable some falling edge interrupts + li t1, 0x0000FFFF + sw t1, 0x20(t0) +Intr02BEEF0A: + # lower some pins + li t1, 0x33000033 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # lower pins whose fall IEs are disabled + # and raise a bunch of other pins + # should not cause an interrupt + li t1, 0x00CCCC33 + sw t1, 0x0C(t0) +Intr02BEEF0B: + # lower pins whose fall IEs are enabled + li t1, 0x00CCCC00 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # =========== High Interrupts =========== + # disable all falling edge interrupts + li t1, 0 + sw t1, 0x20(t0) + # enable some high_ie's for low pins + # should not cause an interrupt + li t1, 0xFF0000FF + sw t1, 0x28(t0) +Intr02BEEF0C: + # enable some high_ie's for high pins + li t1, 0x0000FFFF + sw t1, 0x28(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # lower all pins + li t1, 0 + sw t1, 0x0C(t0) + # lower any existing high_ip's + li t1, 0xFFFFFFFF + sw t1, 0x2C(t0) + # re-enable some high_ie's + li t1, 0xFFFF0000 + sw t1, 0x28(t0) + # raise some pins whose high_ie's are disabled + li t1, 0x0000CCCC + sw t1, 0x0C(t0) + # disable some inputs + li t1, 0xFF00FFFF + sw t1, 0x04(t0) + # raise some pins whose inputs are disabled + li t1, 0x00CCCCCC + sw t1, 0x0C(t0) +Intr02BEEF0D: + # raise some pins whose high_ie's and inputs are enabled + li t1, 0xCCCCCCCC + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # =========== Low Interrupts =========== + # disable all high interrupts + li t1, 0 + sw t1, 0x28(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable some low_ie's for high pins + # should not cause an interrupt + li t1, 0xCC0000CC + sw t1, 0x30(t0) +Intr02BEEF0E: + # enable some low_ie's for low pins + li t1, 0xCCCCFFFF + sw t1, 0x30(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # raise all pins + li t1, 0xFFFFFFFF + sw t1, 0x0C(t0) + # lower any existing low_ip's + # actually takes a little time for vals + # to propagate through synchronizer + # so this extra load is a nop effectively + li t1, 0xFFFFFFFF + sw t1, 0x34(t0) + # re-enable some low_ie's + li t1, 0xFF0000FF + sw t1, 0x30(t0) + # lower some pins whose low_ie's are disabled + li t1, 0xFF1111FF + sw t1, 0x0C(t0) +Intr02BEEF0F: + # disable some inputs of pins whose low_ie's are enabled + li t1, 0x0000FFFF + sw t1, 0x04(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Clear GPIO State ========== + # disable all interrupts + sw x0, 0x18(t0) + sw x0, 0x20(t0) + sw x0, 0x28(t0) + sw x0, 0x30(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # set initial output state + sw x0, 0x0C(t0) + # clear all pending interrupts + li t1, 0xFFFFFFFF + sw t1, 0x1C(t0) + sw t1, 0x24(t0) + sw t1, 0x2C(t0) + sw t1, 0x34(t0) + # ========== Output XOR Test ========== + # enable some inputs + li t1, 0x0000FFFF + sw t1, 0x04(t0) + # enable some outputs + li t1, 0xFF0000FF + sw t1, 0x08(t0) + # enable all rising and falling edge interrupts + li t1, 0xFFFFFFFF + sw t1, 0x18(t0) + sw t1, 0x20(t0) +Intr02BEEF10: + # XOR all outputs + li t1, 0xFFFFFFFF + sw t1, 0x40(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 +Intr02BEEF11: + # XOR some outputs + li t1, 0x33333333 + sw t1, 0x40(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Clear GPIO State ========== + # disable all interrupts + sw x0, 0x18(t0) + sw x0, 0x20(t0) + sw x0, 0x28(t0) + sw x0, 0x30(t0) + # enable all inputs + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # enable all outputs + li t1, 0xFFFFFFFF + sw t1, 0x08(t0) + # set initial output state + sw x0, 0x0C(t0) + # clear XOR + li t1, 0x00000000 + sw t1, 0x40(t0) + # clear all pending interrupts + li t1, 0xFFFFFFFF + sw t1, 0x1C(t0) + sw t1, 0x24(t0) + sw t1, 0x2C(t0) + sw t1, 0x34(t0) + + ################################## + ##### Test 3 - UART Testing ##### + ################################## + li a1, 0x03beef00 # group ID + # clear MEIE + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 0xA (UART) priority = 1 + li t0, 0xC000000 + li t1, 1 + sw t1, 0x28(t0) + # enable source 0xA + li t0, 0x0C002000 + li t1, 0b10000000000 + sw t1, 0(t0) + # ========== Transmitter Holding Register Empty Interrupt (THRE) ========== + # MCR: Loop = 1 + li t0, 0x10000000 + li t1, 0b00010000 + sb t1, 4(t0) + # LCR: Use 8 data bits plus odd parity bit + li t1, 0b00001011 + sb t1, 3(t0) + # IER: Disable all interrupts for now + li t1, 0x0 + sb t1, 1(t0) + # set MEIE + li t1, 0x800 + csrrs x0, mie, t1 + # THR: TX 'l' + li t1, 'l' + sb t1, 0(t0) + # wait directly on UART for completion + li t1, 0b01100001 + 1: lb t2, 5(t0) + bne t1, t2, 1b +Intr03BEEF12: + # IER: enable THR empty intr (ETBEI) + li t1, 0b00000010 + sb t1, 1(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # IER: disable THR empty intr (ETBEI) + sb x0, 1(t0) + # THR: TX 'l' + li t1, 'l' + sb t1, 0(t0) + # THR: TX 'o' + li t1, 'o' + sb t1, 0(t0) +Intr03BEEF13: + # IER: enable THR empty intr (ETBEI) + li t1, 0b00000010 + sb t1, 1(t0) + # This will take a few cycles before UART finishes TX'ing + # If we see SCR modifications in output, it means UART probably + # did wait until empty THR before triggering the interrupt. + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ========== + # Clear SCR + sb x0, 7(t0) +Intr03BEEF14: + # IER: enable RBR ready intr ERBFI + li t1, 0x1 + sb t1, 1(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr03BEEF15: + # THR: TX ' ' + li t1, 0x20 + sb t1, 0(t0) + # This will take a few cycles before UART finishes RX'ing + # If we see SCR modifications in output, it means UART probably + # did wait until received data available before triggering the interrupt. + li t1, 3 + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr03BEEF16: + # THR: TX 't' + li t1, 't' + sb t1, 0(t0) + # Same shenanigans as before, only now we also confirm + # that you can read the RBR before new data is available + # without messing up the receive interrupt. + lb t1, 0(t0) + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # MCR: Loop = 0 + li t1, 0b00000000 + sb t1, 4(t0) + # Clear SCR + sb x0, 7(t0) + # THR: TX 'h' + # should TX but not not trigger interrupt + li t1, 'h' + sb t1, 0(t0) + # wait directly on UART for completion + li t1, 0b01100000 + 1: lb t2, 5(t0) + bne t1, t2, 1b + # Can use THRE test from before to verify we are transmitting + # THR: TX 'e' + li t1, 'e' + sb t1, 0(t0) + # THR: TX 'r' + li t1, 'r' + sb t1, 0(t0) +Intr03BEEF17: + # IER: enable THR empty intr (ETBEI) and RBR ready intr (ERBFI) + li t1, 0b00000011 + sb t1, 1(t0) + sb t1, 7(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # manually wait until transmitter finishes before enabling loop mode + li t1, 0b01100000 + 1: lb t2, 5(t0) + bne t1, t2, 1b + # MCR: Loop = 1 + li t1, 0b00010000 + sb t1, 4(t0) +Intr03BEEF18: +Intr03BEEF19: + # THR: TX 'e' + li t1, 'e' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # wait to finish again + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + # ========== Receiver Line Status Intr (ELSI) & Overrun Error (OE) ========== + # IER: Enable Receiver Line Status Intr (ELSI) + li t1, 0b00000100 + sb t1, 1(t0) + li t1, 0xFF + sb t1, 7(t0) + # We can't cause all kinds of interesting errors, but at least we can + # cause an overrun error by transmitting twice without reading. +Intr03BEEF1A: + # THR: TX '\n' + li t1, 0xD + sb t1, 0(t0) + # THR: TX 'G' + li t1, 'G' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 + + #################################################### + ##### Test 4 - Signs of Life on PLIC Context 1 ##### + #################################################### + li a1, 0x04beef00 # group ID + # clear MEIE (good to turn off while configuring peripherals) + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 3 (GPIO) priority = 6 + li t0, 0xC000000 + li t1, 6 + sw t1, 0x0C(t0) + # source 0xA (UART) priority = 7 + li t1, 7 + sw t1, 0x28(t0) + # disable sources 3,0xA on context 0 + li t0, 0x0C002000 + li t1, 0 + sw t1, 0(t0) + # enable sources 3,0xA on context 1 + li t0, 0x0C002080 + li t1, 0b10000001000 + sw t1, 0(t0) + # ========== Configure UART ========== + # MCR: Loop = 1 + li t0, 0x10000000 + li t1, 0b10000 + sb t1, 4(t0) + # LCR: Use 8 data bits plus odd parity bit + li t1, 0b00001011 + sb t1, 3(t0) + # IER: Enable Received Data Available Interrupt + li t1, 0x01 + sb t1, 1(t0) + # ========== Configure GPIO ========== + # raise all input_en + li t0, 0x10060000 + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # raise all output_en + sw t1, 0x08(t0) + # raise all rise_en + sw t1, 0x18(t0) + # ========== Execute Test ========== + # set MEIE and SEIE + li t0, 0xA00 + csrrs x0, mie, t0 +Intr04BEEF1B: + # UART TX 'e' + li t0, 0x10000000 + li t1, 'e' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr04BEEF1C: + # GPIO raise pin 19 + li t0, 0x10060000 + li t1, 0x00080000 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # Now let's go bonkers and trigger both! +Intr04BEEF1D: + # TX 'n' + li t0, 0x10000000 + li t1, 'n' + sb t1, 0(t0) +Intr04BEEF1E: + # GPIO lower pin 19 raise pin 0 + li t0, 0x10060000 + li t1, 0x00000001 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00011000 + 1: bne t1,a0,1b + li a0, 0 + # --------------------------------------------------------------------------------------------- + +//terminate_test: +// li a0, 2 // Trap handler behavior (go to machine mode) +// ecall // writes mcause to the output. +// csrw mtvec, x4 // restore original trap handler to halt program + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# stack memory (size 16 words) +.align 3 +stack: +.fill 16, 8, 0xdeadbeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +# signature output +wally_signature: +.fill 0x200, 8, 0x00000000 +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S new file mode 100644 index 000000000..dd412abe7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S @@ -0,0 +1,51 @@ +/////////////////////////////////////////// +// +// WALLY-MMU +// +// Author: Kip Macsai-Goren +// +// Created 2022-11-18 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid) + +INIT_TESTS + +TRAP_HANDLER m + +la t4, pre_trap +csrw mtvec, t4 // set the new trap handler to do the pre behavior first. + +GOTO_S_MODE // go to S mode to attempt to turn on virtual memory + +la ra, post_satp // load the address after the failing adress into ra so it doesn't get confused +GOTO_SV32 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invlaid address. Should cause invalid instruction exception + +post_satp: + j test_end + +pre_trap: + csrwi satp, 0x0 // zero out the satp, turning off virtual memory with incorrect address, then jumping to the normal trap handler. + j trap_handler_m + +test_end: + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output new file mode 100644 index 000000000..723617745 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output @@ -0,0 +1,18 @@ +00000000 # msip zero on reset +00000000 +00000000 # mip is zero +00000000 +00000008 # mip msip bit is set +00000000 +00000000 # mip msip bit is reset +00000000 +00000000 # mip mtip bit is reset +00000000 +FFFFFFFF # mtimecmp is same as written value +FFFFFFFF +A5A5A5A5 # mtimecmph is same as written value +FFFFFFFF +00000000 # mip mtip is zero +00000000 +00000080 # mip mtip is set +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-gpio-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-gpio-01.reference_output new file mode 100644 index 000000000..2da377bd8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-gpio-01.reference_output @@ -0,0 +1,81 @@ + +00000000 # reset to zero tests: input_val +00000000 +00000000 # input_en +00000000 +00000000 # output_en +00000000 +00000000 # output_val +00000000 +00000000 # rise_ie +00000000 +00000000 # fall_ie +00000000 +00000000 # low_ie +00000000 +00000000 # high_ie +00000000 +00000000 # rise_ip +00000000 +00000000 # fall_ip +00000000 +00000000 # high_ip +00000000 +ffffffff # low_ip +ffffffff +00000000 # out_xor +00000000 +A5A5A5A5 # test output pins +ffffffff +5A5AFFFF +00000000 +00000000 # test input enables +00000000 +5A5A0000 +00000000 +A55A0000 # test XOR +ffffffff +A55A0000 # Test interrupt pending bits: high_ip +ffffffff +5AA5FFFF # low_ip +00000000 +00000000 # rise_ip +00000000 +00000000 # fall_ip +00000000 +A4AA0000 # input_val +ffffffff +A5FA0000 # high_ip +ffffffff +5BF5FFFF # low_ip +00000000 +00A00000 # rise_ip +00000000 +01500000 # fall_ip +00000000 +00000000 # MEIP +00000000 +00000000 # Test interrupts can be enabled without being triggered: MIP = 0 +00000000 +00000000 # MIP = 0 +00000000 +00000000 # MIP = 0 +00000000 +00000000 # MIP = 0 +00000000 +00000800 # Test interrupts can be enabled and triggered: MEIP set from high_ie +00000000 +00000000 # MEIP = 0 +00000000 +00000800 # MEIP set from low_ie +00000000 +00000000 # MEIP = 0 +00000000 +00000800 # MEIP set from rise_ie +00000000 +00000000 # MEIP = 0 +00000000 +00000800 # MEIP set from fall_ie +00000000 +00000000 # MEIP = 0 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output new file mode 100644 index 000000000..c6c6fa7f9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output @@ -0,0 +1,498 @@ +00000000 # read empty MIP (1.0.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # Claim gives no interrupt due to zero priority +00000000 +00000008 # interrupt still pending due to no claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.0.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.0.2) +00000000 +00000000 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # claim gives no interrupt due to no intPending +00000000 +00000000 # no interrupts pending after clear +00000000 +00000000 # still no interrupts after clear +00000000 +00000000 # read empty MIP (1.1.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # interrupt still pending due to no claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.1.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.2.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.2.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.3.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.3.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.4.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.4.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.5.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.5.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.6.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.6.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.7.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (2.0) +00000000 +00000408 # gpio and uart pending +00000000 +00000003 # claim gpio +00000000 +00000400 # gpio no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000800 # MEIP set (2.1) +00000000 +00000408 # gpio and uart pending +00000000 +00000003 # claim gpio +00000000 +00000400 # gpio no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000800 # MEIP set (2.2) +00000000 +00000408 # gpio and uart pending +00000000 +0000000A # claim uart +00000000 +00000008 # uart no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000800 # MEIP set (2.3) +00000000 +00000408 # gpio and uart pending +00000000 +0000000A # claim uart +00000000 +00000008 # uart no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000000 # MEIP empty (2.4) +00000000 +00000408 # gpio and uart pending +00000000 +0000000A # claim none +00000000 +00000008 # gpio and uart still pending +00000000 +00000000 # no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (3.0) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (3.1) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (3.2) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # GPIO interrupt pending after UART claimcomp +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (3.3) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # check UART interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (4.0) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (4.1) +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (4.2) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (4.3) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (4.4) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (4.5) +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # All disabled (4.6) +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (5.0) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (5.1) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (5.2) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (5.3) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (5.4) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (5.5) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (5.6) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +0000000b # written due to goto_s_mode +00000000 +00000200 # read sip (7.0) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.1) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.2) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # GPIO interrupt pending after UART claimcomp +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.3) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read sip (7.4) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # nothing in claim register +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.5) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read sip (7.6) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # nothing in claim register +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # check no interrupts pending +00000000 +00000009 # output from ecall in supervisor mode +00000000 +00000800 # MEIP set (8.0) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # GPIO interrupt pending after UART claimcomp +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # read empty MIP # no interrupts, meip is low +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set +00000000 +00000008 # GPIO interrupt pending after complete +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # read empty MIP # meip is zeroed +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000800 # MEIP set +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output new file mode 100644 index 000000000..da4f81fab --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output @@ -0,0 +1,79 @@ +0000000b # ecall for change to supervisor mode +00000000 + +00000200 # 1.1: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000200 # 1.2: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.3: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # No claim +00000000 +00000008 # Interrupt unclaimed and still pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.4: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # No claim +00000000 +00000008 # Interrupt unclaimed and still pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.5: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context even though it is masked by priority +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000200 # 1.6: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.7: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Glaim GPIO in supervisor conxtex even though it is masked by priority +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output new file mode 100644 index 000000000..ebac64f92 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output @@ -0,0 +1,150 @@ +00000000 # Reset tests +00000000 +00000001 # 00000000 *** commented because LCR should reset to zero but resets to 3 due to the FPGA +00000000 +00000000 +00000000 +00000060 +00000000 +00000000 +00000000 +00000060 # read-write test +00000000 +00000020 # transmitter register empty but shift register not +00000000 +00000101 # transmitter is not empty when done transmitting 5 bits +00000000 +00000000 +00000000 +00000060 +00000000 +00000101 # Multi-bit transmission: 5 bits +00000000 +00000015 +00000000 +00000101 # Transmit 6 bits +00000000 +0000002A +00000000 +00000101 # Transmit 7 bits +00000000 +0000007F +00000000 +00000101 # Transmit 8 bits +00000000 +ffffff80 +ffffffff +00000101 # Odd parity +00000000 +00000079 +00000000 +00000101 # Even parity +00000000 +0000006A +00000000 +00000101 # Extra stop bit +00000000 +0000005B +00000000 +00000002 # Transmission interrupt tests +00000000 +00000401 # Interrupt generated by finished transmission +00000000 +00000004 +00000000 +00000006 # IIR return LSR intr and LSR has an overflow error +00000000 +00000063 +00000000 +00000004 +00000000 +00000001 +00000000 +00000001 # MODEM interrupt tests +00000000 +00000000 +00000000 +00000011 +00000000 +00000001 +00000000 +00000000 # DSR Test +00000000 +00000032 +00000000 +00000001 +00000000 +00000000 # RI Test +00000000 +00000034 +00000000 +00000001 +00000000 +00000000 # DCD Test +00000000 +ffffffB8 +ffffffff +00000001 +00000000 +ffffffC2 # FIFO interrupt +ffffffff +0000C101 +00000000 +00000000 +00000000 +ffffffC1 +ffffffff +0000C401 +00000000 +ffffffA5 +ffffffff +ffffffC1 +ffffffff +00000001 +00000000 +00000002 +00000000 +00000061 +00000000 +00000003 +00000000 +00000060 +00000000 +0000C101 +00000000 +ffffffC1 +ffffffff +00000060 +00000000 +ffffffC1 # FIFO filling/overrun test +ffffffff +0000C401 # Threshold = 1 +00000000 +ffffffC1 # Threshold = 4 +ffffffff +0000C101 +00000000 +0000C401 +00000000 +ffffffC1 # Threshold = 8 +ffffffff +0000C101 +00000000 +0000C401 +00000000 +ffffffC1 # Threshold = 14 +ffffffff +0000C101 +00000000 +0000C401 +00000000 +0000C101 +00000000 +00000061 # FIFO has data, no overrun +00000000 +00000006 # wait for interrupt +00000000 +ffffffA3 # FIFO overrun error +ffffffff +0000000b # ecall from test termination +00000000 \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 60872449e..a0691f2b4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -873,12 +873,12 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .equ PLIC_THRESH1, 0x0C201000 # Priority threshold for context 1 (supervisor mode) .equ PLIC_CLAIM1, 0x0C201004 # Claim/Complete register for context 1 - .4byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts - .4byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts - .4byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority - .4byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority - .4byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode - .4byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode + .8byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts + .8byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts + .8byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority + .8byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority + .8byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode + .8byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode .endm .macro END_TESTS @@ -1008,20 +1008,141 @@ read08_test: addi a6, a6, 8 j test_loop // go to next test case + +read04_test: + // address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal). + li t2, 0xBAD // bad value that will be overwritten on good reads. + lb t2, 0(t3) + andi t2, t2, 0xF // mask lower 4 bits + sd t2, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 + j test_loop // go to next test case + readmip_test: // read the MIP into the signature csrr t2, mip - sw t2, 0(t1) - addi t1, t1, 4 - addi a6, a6, 4 + sd t2, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 j test_loop // go to next test case readsip_test: // read the MIP into the signature csrr t2, sip - sw t2, 0(t1) - addi t1, t1, 4 - addi a6, a6, 4 + sd t2, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 j test_loop // go to next test case +claim_m_plic_interrupts: // clears one non-pending PLIC interrupt + li t2, 0x0C00000C // GPIO priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C000028 // UART priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C002000 + li t3, 0x0C200004 + li t4, 0xFFF + lw t6, 0(t2) // save current enable status + sw t4, 0(t2) // enable all relevant interrupts on PLIC + lw t5, 0(t3) // make PLIC claim + sw t5, 0(t3) // complete claim made + sw t6, 0(t2) // restore saved enable status + li t2, 0x0C00000C // GPIO priority + li t3, 0x0C000028 // UART priority + lw t4, 4(sp) // load stored GPIO and UART priority + lw t5, 0(sp) + addi sp, sp, 8 // restore stack pointer + sw t4, 0(t2) + sw t5, 0(t3) + j test_loop + +claim_s_plic_interrupts: // clears one non-pending PLIC interrupt + li t2, 0x0C00000C // GPIO priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C000028 // UART priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C002080 + li t3, 0x0C201004 + li t4, 0xFFF + lw t6, 0(t2) // save current enable status + sw t4, 0(t2) // enable all relevant interrupts on PLIC + lw t5, 0(t3) // make PLIC claim + sw t5, 0(t3) // complete claim made + sw t6, 0(t2) // restore saved enable status + li t2, 0x0C00000C // GPIO priority + li t3, 0x0C000028 // UART priority + lw t4, 4(sp) // load stored GPIO and UART priority + lw t5, 0(sp) + addi sp, sp, 8 // restore stack pointer + sw t4, 0(t2) + sw t5, 0(t3) + j test_loop + +uart_lsr_intr_wait: // waits for interrupts to be ready + li t2, 0x10000002 // IIR + li t4, 0x6 +uart_lsr_intr_loop: + lb t3, 0(t2) + andi t3, t3, 0x7 + bne t3, t4, uart_lsr_intr_loop +uart_save_iir_status: + sd t3, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 + j test_loop + +uart_data_wait: + li t2, 0x10000005 // LSR + li t3, 0x10000002 // IIR + li a4, 0x61 +uart_read_LSR_IIR: + lbu t4, 0(t3) // save IIR before reading LSR might clear it + // check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this. + li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending + beq t4, t5, uart_rxfifo_timout + lb t5, 0(t2) // read LSR + andi t6, t5, 0x61 // wait until all transmissions are done and data is ready + bne a4, t6, uart_read_LSR_IIR + j uart_data_ready +uart_rxfifo_timout: + li t4, 0x10000000 // read from the fifo to clear the rx timeout error + lb t5, 0(t4) + sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur. + //read the fifo until empty + j uart_read_LSR_IIR + + +uart_data_ready: + li t2, 0 + sd t2, 0(t1) // clear entry deadbeef from memory + lbu t4, 0(t3) // re read IIR + andi t5, t5, 0x9F // mask THRE and TEMT from signature + sb t4, 1(t1) // IIR + sb t5, 0(t1) // LSR + addi t1, t1, 8 + addi a6, a6, 8 + j test_loop + +uart_clearmodemintr: + li t2, 0x10000006 + lb t2, 0(t2) + j test_loop + goto_s_mode: // return to address in t3, li a0, 3 // Trap handler behavior (go to supervisor mode) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S new file mode 100644 index 000000000..838e4654d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S @@ -0,0 +1,95 @@ +/////////////////////////////////////////// +// +// WALLY-gpio +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 3 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define CLINT registers =========== + +.equ CLINT, 0x02000000 +.equ msip, (CLINT+0x00) +.equ mtimecmp, (CLINT+0x4000) # doesn't necessarily reset to zero +.equ mtimecmph,(CLINT+0x4004) +.equ mtime, (CLINT+0xBFF8) # resets to zero but cannot be easily tested +.equ mtimeh, (CLINT+0xBFFC) + +# =========== Verify verifiable registers reset to zero =========== + +.8byte msip, 0x00000000, read32_test # msip reset to zero + +# =========== msip tests =========== + +.8byte msip, 0xFFFFFFFE, write32_test # write to invalid bits of msip +.8byte 0x0, 0x00000000, readmip_test # msip bit should be zero +.8byte msip, 0x00000001, write32_test # set msip to one +.8byte 0x0, 0x00000008, readmip_test # msip bit is set +.8byte msip, 0x00000000, write32_test # set msip to zero +.8byte 0x0, 0x00000000, readmip_test # msip bit is released + +# =========== mtime write tests =========== + +.8byte mtime, 0x00000000, write32_test # test we can write to mtime +.8byte mtimeh, 0x00000000, write32_test # test we can write to mtimeh +.8byte 0x0,0x00000000, readmip_test # mtip bit should be zero + +# =========== mtimecmp tests =========== + +.8byte mtimecmp, 0xFFFFFFFF, write32_test # verify mtimecmp is writable +.8byte mtimecmph, 0xA5A5A5A5, write32_test # verify mtimecmph is writable +.8byte mtimecmp, 0xFFFFFFFF, read32_test # read back value written to mtimecmp +.8byte mtimecmph, 0xA5A5A5A5, read32_test # read back value written to mtimecmph +.8byte mtime, 0xFFFFFFFF, write32_test # write to mtime +.8byte 0x0, 0x00000000, readmip_test # mtip should still be zero +.8byte mtimeh, 0xA5A5A5A6, write32_test # cause mtip to go high by making mtime > mtimecmp +.8byte 0x0, 0x00000080, readmip_test # mtip should be set + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S new file mode 100644 index 000000000..6e3ebcbcb --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S @@ -0,0 +1,164 @@ +/////////////////////////////////////////// +// +// WALLY-gpio +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 3 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Verify all registers reset to zero =========== + +.8byte input_val, 0x00000000, read32_test # input_val reset to zero +.8byte input_en, 0x00000000, read32_test # input_en reset to zero +.8byte output_en, 0x00000000, read32_test # output_en reset to zero +.8byte output_val, 0x00000000, read32_test # output_val reset to zero +.8byte rise_ie, 0x00000000, read32_test # rise_ie reset to zero +.8byte fall_ie, 0x00000000, read32_test # fall_ie reset to zero +.8byte high_ie, 0x00000000, read32_test # high_ie reset to zero +.8byte low_ie, 0x00000000, read32_test # low_ie reset to zero +.8byte rise_ip, 0x00000000, read32_test # rise_ip reset to zero +.8byte fall_ip, 0x00000000, read32_test # fall_ip reset to zero +.8byte high_ip, 0x00000000, read32_test # high_ip reset to zero +.8byte low_ip, 0xffffffff, read32_test # low_ip reset to ones since all zeroes +.8byte out_xor, 0x00000000, read32_test # out_xor reset to zero + +# =========== Test output and input pins =========== + +.8byte output_en, 0xFFFFFFFF, write32_test # enable all output pins +.8byte output_val, 0xA5A5A5A5, write32_test # write alternating pattern to output pins +.8byte input_en, 0xFFFFFFFF, write32_test # enable all input pins +.8byte input_val, 0xA5A5A5A5, read32_test # read pattern from output pins +.8byte output_val, 0x5A5AFFFF, write32_test # write different pattern to output pins +.8byte input_val, 0x5A5AFFFF, read32_test # read different pattern from output pins + +# =========== Test input enables =========== +.8byte input_en, 0x00000000, write32_test # disable all input pins +.8byte input_val, 0x00000000, read32_test # read 0 since input pins are disabled +.8byte input_en, 0xFFFF0000, write32_test # enable a few input pins +.8byte input_val, 0x5A5A0000, read32_test # read part of pattern set above. + + +# =========== Test XOR functionality =========== +.8byte out_xor, 0xFF00FF00, write32_test # invert certain pin values +.8byte input_val, 0xA55A0000, read32_test # read inverted pins and verify input enable is working + +# =========== Test Interrupt Pending bits =========== + +SETUP_PLIC + +.8byte low_ip, 0xFFFFFFFF, write32_test # clear pending low interrupts +.8byte high_ip, 0xFFFFFFFF, write32_test # clear pending high interrupts +.8byte rise_ip, 0xFFFFFFFF, write32_test # clear pending rise interrupts +.8byte fall_ip, 0xFFFFFFFF, write32_test # clear pending fall interrupts +.8byte high_ip, 0xA55A0000, read32_test # check pending high interrupts +.8byte low_ip, 0x5AA5FFFF, read32_test # check pending low interrupts +.8byte rise_ip, 0x00000000, read32_test # check pending rise interrupts +.8byte fall_ip, 0x00000000, read32_test # check pending fall interrupts +.8byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts +.8byte input_val, 0xA4AA0000, read32_test # check new output matches expected output +.8byte high_ip, 0xA5FA0000, read32_test # high interrupt pending +.8byte low_ip, 0x5BF5FFFF, read32_test # low interrupt pending should be opposite high for enabled pins +.8byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising) +.8byte fall_ip, 0x01500000, read32_test # check for changed bits (falling) +.8byte 0x0, 0x00000000, readmip_test # Check no external interrupt has been generated + +# =========== Test interrupts can be enabled without being triggered =========== + +.8byte high_ie, 0x00010000, write32_test # enable high interrupt on bit 16, no pending interrupt +.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending +.8byte low_ie, 0x00020000, write32_test # enable low interrupt on bit 17, no pending interrupt +.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending +.8byte rise_ie, 0x00010000, write32_test # enable rise interrupt on bit 16, no pending interrupt +.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending +.8byte fall_ie, 0x00010000, write32_test # enable fall interrupt on bit 16, no pending interrupt +.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending + +# =========== Test interrupts can be enabled and triggered =========== + +.8byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending +.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.8byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17 +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.8byte 0x0, 0x00000000, readmip_test # MEIP should be released +.8byte low_ie, 0x00010000, write32_test # enable low interrupt on bit 16, which is pending +.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.8byte low_ie, 0x00000000, write32_test # disable low interrupt on bit 16 +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.8byte 0x0, 0x00000000, readmip_test # MEIP should be released +.8byte rise_ie, 0x00200000, write32_test # enable rise interrupt on bit 21, which is pending +.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.8byte rise_ie, 0x00000000, write32_test # disable rise interrupt on bit 21, which is pending +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.8byte 0x0, 0x00000000, readmip_test # MEIP should be released +.8byte fall_ie, 0x01000000, write32_test # enable high interrupt on bit 24, which is pending +.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.8byte fall_ie, 0x00000000, write32_test # disable high interrupt on bit 24, which is pending +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.8byte 0x0, 0x00000000, readmip_test # MEIP should be released + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S new file mode 100644 index 000000000..43ceabfcf --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S @@ -0,0 +1,954 @@ +/////////////////////////////////////////// +// +// WALLY-plic +// +// Author: Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define PLIC registers =========== + +.equ PLIC, 0x0C000000 +.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3 +.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10 +.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register +.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1 +.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1 +.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode) +.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0 +.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode) +.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1 + +# =========== Define GPIO registers =========== + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Define UART registers =========== + +.equ UART, 0x10000000 +.equ UART_IER, (UART+0x01) +.equ UART_MCR, (UART+0x04) +.equ UART_MSR, (UART+0x06) + +# =========== Initialize UART and GPIO =========== + +# GPIO Initialization +.8byte input_en, 0x00000001, write32_test # enable bit 0 of input_en +.8byte output_en, 0x00000001, write32_test # enable bit 0 of output_en +.8byte output_val, 0x00000000, write32_test # make sure output_val is 0 +.8byte rise_ie, 0x00000001, write32_test # enable rise interrupts + +# =========== Initialize relevant PLIC registers =========== + +.8byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero +.8byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max + +# =========== Machine-Mode Priority Testing (1.T.X) =========== + +# Test 1.0.0: GPIO int lacks priority (0 = 0) +.8byte PLIC_THRESH0, 0x00000000, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +#.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.0.1: GPIO int has priority (1 > 0) +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.0.2: meip and c/c clear without interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.1.0: GPIO lacks priority (1 = 1) +.8byte PLIC_THRESH0, 0x00000001, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.1.1: GPIO int has priority (2 > 1) +.8byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.2.0: GPIO int lacks priority (2 = 2) +.8byte PLIC_THRESH0, 0x00000002, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.2.1: GPIO int has priority (3 > 2) +.8byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.3.0: GPIO int lacks priority (3 = 3) +.8byte PLIC_THRESH0, 0x00000003, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.3.1: GPIO int has priority (4 > 3) +.8byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.4.0: GPIO int lacks priority (4 = 4) +.8byte PLIC_THRESH0, 0x00000004, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.4.1: GPIO int has priority (5 > 4) +.8byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.5.0: GPIO int lacks priority (5 = 5) +.8byte PLIC_THRESH0, 0x00000005, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.5.1: GPIO int has priority (6 > 5) +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.6.0: GPIO int lacks priority (6 = 6) +.8byte PLIC_THRESH0, 0x00000006, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.6.1: GPIO int has priority (7 > 6) +.8byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.7.0: GPIO int lacks priority (7 = 7) +.8byte PLIC_THRESH0, 0x00000007, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# =========== UART vs GPIO priority (2.X) =========== + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max +# UART Initialization +.8byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS +.8byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0 +.8byte UART_MSR, 0x00, write08_test # disable UART interrupt + +# Test 2.0: GPIO Priority = UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.1: GPIO Priority > UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3 +.8byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.2: GPIO Priority < UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4 +.8byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.3: GPIO Priority < UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6 +.8byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.4: Interrupts don't have enough priority + +.8byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4 +.8byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5 +.8byte PLIC_THRESH0, 0x00000006, write32_test # set m-mode threshold to 6 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== SEIP tests (3.X) =========== + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 + +# Test 3.0: Cause machine and supervisor interrupts + +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1 +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.1: Suppress machine mode interrupts + +.8byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3 +.8byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2 +.8byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.2: Cause SEIP with UART first + +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6 +.8byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7 +.8byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.3: Low SEIP due to insufficient priority + +.8byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIOPriority = 2 +.8byte PLIC_INTPRI_UART, 0x00000003, write32_test # UARTPriority = 3 +.8byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 4 +.8byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== UART interrupt enable tests (4.X) =========== + +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 4.0: GPIO m-mode disabled + +.8byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.1: UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.2: GPIO s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.3: UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.4: GPIO and UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.5: GPIO and UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.6: GPIO and UART fully disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== GPIO interrupt enable tests (5.X) =========== + +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 5.0: GPIO m-mode disabled + +.8byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.1: UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.2: GPIO s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.3: UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.4: GPIO and UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.5: GPIO and UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.6: GPIO and UART fully disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== S-mode enable tests (7.X) =========== + +.8byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 7.0: GPIO m-mode disabled + +.8byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.1: UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.2: GPIO s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.3: UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.4: GPIO and UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.5: GPIO and UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.6: GPIO and UART fully disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== Special claim tests (8) =========== + +.8byte 0x0, 0x0, goto_m_mode # write 0x9 to output + +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6 +.8byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7 +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 + +# Test 8 + +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # read interrupt pending +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt cleared +.8byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO +.8byte 0x0, 0x00000000, readmip_test # no interrupts, meip is low +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO +.8byte 0x0, 0x00000800, readmip_test # GPIO interrupt sets MEIP +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # GPIO bit is set +.8byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO again +.8byte 0x0, 0x00000000, readmip_test # meip is zeroed +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete UART claim +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # UART pending +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO claim +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # GPIO and UART pending +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S new file mode 100644 index 000000000..ed5063e86 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S @@ -0,0 +1,230 @@ +/////////////////////////////////////////// +// +// WALLY-plic-s +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// Test PLIC supervisor context interrupts and claim/complete +// +// Created 2022-07-29 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define PLIC registers =========== + +.equ PLIC, 0x0C000000 +.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3 +.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10 +.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register +.equ PLIC_INTPENDING1, (PLIC+0x001004) # intPending0 register +.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1 +.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1 +.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode) +.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0 +.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode) +.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1 + +# =========== Define GPIO registers =========== + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Initialize GPIO =========== + +# GPIO Initialization +.8byte input_en, 0x00000001, write32_test # enable bit 0 of input_en +.8byte output_en, 0x00000001, write32_test # enable bit 0 of output_en +.8byte output_val, 0x00000000, write32_test # make sure output_val is 0 +.8byte rise_ie, 0x00000001, write32_test # enable rise interrupts + +# =========== Initialize relevant PLIC registers =========== + +.8byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to 0 to never interrupt + +# =========== Enter Supervisor Mode =========== + +.8byte 0x0, 0x0, goto_s_mode # Enter supervisor mode + +# =========== Test interrupt enables and priorities =========== + +# Case 1.1: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.2: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.3: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.4: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.5: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.6: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.7: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.8byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# All done + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S new file mode 100644 index 000000000..3cbf3591b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S @@ -0,0 +1,248 @@ +/////////////////////////////////////////// +// +// WALLY-uart +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 + +.equ UART, 0x10000000 +.equ UART_RBR, (UART) +.equ UART_THR, (UART) +.equ UART_IER, (UART+0x01) +.equ UART_IIR, (UART+0x02) +.equ UART_FCR, (UART+0x02) +.equ UART_LCR, (UART+0x03) +.equ UART_MCR, (UART+0x04) +.equ UART_LSR, (UART+0x05) +.equ UART_MSR, (UART+0x06) +.equ UART_Scr, (UART+0x07) + +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== UART resets to correct values on master reset =========== + +.8byte UART_IER, 0x00, read08_test +.8byte UART_IIR, 0x01, read08_test # IIR resets to 1 +# .8byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3 to help Linux boot +.8byte UART_MCR, 0x00, read08_test +.8byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set +.8byte UART_MSR, 0x00, read04_test + +# =========== Basic read-write =========== + +.8byte UART_LCR, 0x00, write08_test # set LCR to initial value +.8byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test +.8byte UART_LSR, 0x60, read08_test +.8byte UART_THR, 0x00, write08_test # write value to UART +.8byte UART_LSR, 0x00, read08_test # data not ready and transmitter is not empty +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and LSR +.8byte UART_RBR, 0x00, read08_test # read written value +.8byte UART_LSR, 0x60, read08_test # read LSR + +# =========== Different size read-write =========== + +# Transmit 5 bits + +.8byte UART_LCR, 0x00, write08_test # set LCR to transmit 5 bits +.8byte UART_THR, 0x55, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x15, read08_test # read written value without bits 5-7 + +# Transmit 6 bits + +.8byte UART_LCR, 0x01, write08_test # set LCR to transmit six bits +.8byte UART_THR, 0xAA, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x2A, read08_test # read written value without bits 6 & 7 + +# Transmit 7 bits + +.8byte UART_LCR, 0x02, write08_test # set LCR to transmit seven bits +.8byte UART_THR, 0xFF, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x7F, read08_test # read written value without bit 7 + +# Transmit 8 bits + +.8byte UART_LCR, 0x03, write08_test # set LCR to transmit eight bits +.8byte UART_THR, 0x80, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x80, read08_test # read full written value + sign extension + +# Check function with odd parity + +.8byte UART_LCR, 0x0B, write08_test # set LCR to transmit 8 bits + odd partiy +.8byte UART_THR, 0x79, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x79, read08_test # read full written value + +# Check function with even parity + +.8byte UART_LCR, 0x1B, write08_test # set LCR to transmit 8 bits + even parity +.8byte UART_THR, 0x6A, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x6A, read08_test # read full written value + +# Check function with extra stop bit + +.8byte UART_LCR, 0x07, write08_test # set LCR to transmit 8 bits + extra stop +.8byte UART_THR, 0x5B, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x5B, read08_test # read full written value +.8byte UART_LCR, 0x03, write08_test # set LCR to transmit 8 bits + no extra stop bit + +# =========== Transmit-related interrupts =========== + +.8byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.8byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt +.8byte UART_THR, 0x00, write08_test # write zeroes to transmitter +.8byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt +.8byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer +.8byte UART_IIR, 0x04, read08_test # data interrupt should still be high +.8byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error. +.8byte UART_LSR, 0x23, read08_test # read overrun error from LSR +.8byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared +.8byte UART_RBR, 0x01, read08_test # read previous value from UART + +# =========== MODEM interrupts =========== + +.8byte UART_MSR, 0x00, write08_test # clear MSR +.8byte UART_IER, 0x08, write08_test # enable MODEM Status interrupts +.8byte UART_IIR, 0x01, read08_test # no interrupts pending +.8byte UART_MCR, 0x12, write08_test # Cause DCTS interrupt +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0x11, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # interrupt cleared by reading MSR +.8byte UART_MCR, 0x13, write08_test # Set DSR high +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0x32, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.8byte UART_MCR, 0x17, write08_test # Set RIb low and keep CTS and DSR +.8byte UART_MCR, 0x13, write08_test # Set RIb high and keep CTS and DSR +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0x34, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.8byte UART_MCR, 0x1B, write08_test # Set DCD high and keep CTS and DSR +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0xb8, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.8byte UART_MCR, 0x10, write08_test # Clear MCR +.8byte UART_MSR, 0x00, write08_test # Clear MSR + +# =========== FIFO interrupts =========== + +.8byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.8byte UART_FCR, 0x41, write08_test # Set FIFO threshold to 4 and enable FIFO mode +.8byte UART_IIR, 0xC2, read08_test # Enabling FIFO sets top two bits of IIR +.8byte UART_THR, 0x00, write08_test # write 0 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # no interrupts pending (transmitter interrupt squashed by early read) +.8byte UART_RBR, 0x00, read08_test # read 0 from buffer register +.8byte UART_THR, 0xA5, write08_test # Write A5 to transmit register +.8byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.8byte UART_IIR, 0xC1, read08_test # no interrupts pending +.8byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.8byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to data ready +.8byte UART_RBR, 0xA5, read08_test # Read A5 from buffer register +.8byte UART_IIR, 0xC2, read08_test # Data ready interrupt cleared +.8byte UART_RBR, 0x01, read08_test # Read 1 from buffer register +.8byte UART_RBR, 0x02, read08_test # Read 2 from buffer register +.8byte UART_LSR, 0x61, read08_test # Data ready, 1 item left in FIFO +.8byte UART_RBR, 0x03, read08_test # Read 3 from buffer register +.8byte UART_LSR, 0x60, read08_test # No data ready, FIFO is empty +.8byte UART_THR, 0xFF, write08_test # Write FF to transmit register +.8byte UART_THR, 0xFE, write08_test # Write FE to transmit register +.8byte 0x0, 0xC101, uart_data_wait # Interrupt due to data ready +.8byte UART_FCR, 0xC7, write08_test # Clear all bytes in FIFO +.8byte UART_FCR, 0xC1, read08_test # Check that FCR clears bits 1 and 2 when written to 1 +.8byte UART_LSR, 0x60, read08_test # No data ready, FIFO cleared by writing to FCR + +# =========== FIFO receiver/overrun =========== + +.8byte UART_FCR, 0x01, write08_test # Set FIFO trigger threshold to 1 and enable FIFO mode +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger level +.8byte UART_THR, 0x00, write08_test # Write 0 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_FCR, 0x41, write08_test # Set FIFO trigger threshold to 4 +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.8byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.8byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.8byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_FCR, 0x81, write08_test # Set FIFO trigger threshold to 8 +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.8byte UART_THR, 0x04, write08_test # Write 4 to transmit register +.8byte UART_THR, 0x05, write08_test # Write 5 to transmit register +.8byte UART_THR, 0x06, write08_test # Write 6 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.8byte UART_THR, 0x07, write08_test # Write 7 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_FCR, 0xC1, write08_test # Set FIFO trigger threshold to 14 +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.8byte UART_THR, 0x08, write08_test # Write 8 to transmit register +.8byte UART_THR, 0x09, write08_test # Write 9 to transmit register +.8byte UART_THR, 0x0A, write08_test # Write 10 to transmit register +.8byte UART_THR, 0x0B, write08_test # Write 11 to transmit register +.8byte UART_THR, 0x0C, write08_test # Write 12 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.8byte UART_THR, 0x0D, write08_test # Write 13 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_THR, 0x0E, write08_test # Write 14 to transmit register +.8byte UART_THR, 0x0F, write08_test # Write 15 to transmit register +.8byte 0x0, 0xC101, uart_data_wait +.8byte UART_LSR, 0x61, read08_test # FIFO contains data, no overrun error +.8byte UART_THR, 0x10, write08_test # Write 16 to transmit register, filling RX shift register +.8byte UART_THR, 0x11, write08_test # Write 17 to transmit register, destroying contents held in shift register +.8byte 0x0, 0x06, uart_lsr_intr_wait # Wait for LSR interrupt ID +.8byte UART_LSR, 0xA3, read08_test # Read overrun error from LSR + +.8byte 0x0, 0x0, terminate_test \ No newline at end of file