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fix UART RX FIFO bug where tail pointer can overtake head pointer

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bbracker 2021-07-22 02:09:41 -04:00
parent cdcf419147
commit 9dcd5d3622
4 changed files with 33 additions and 24697 deletions
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1
wally-pipelined/config/buildroot/wally-config.vh
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@ -31,6 +31,7 @@
`define BUSYBEAR 0 `define BUSYBEAR 0
`define LINUX_FIX_READ {'h10000005} `define LINUX_FIX_READ {'h10000005}
`define LINUX_TEST_VECTORS "../linux-testgen/linux-testvectors/" `define LINUX_TEST_VECTORS "../linux-testgen/linux-testvectors/"
//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
// RV32 or RV64: XLEN = 32 or 64 // RV32 or RV64: XLEN = 32 or 64
`define XLEN 64 `define XLEN 64

11
wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog
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@ -1,14 +1,11 @@
set pagination off set pagination off
target extended-remote :1236 target extended-remote :1236
file ../buildroot-image-output/vmlinux file ../buildroot-image-output/vmlinux
#b do_idle stepi 1000
#c b do_idle
#c c
#c c
#c
b *0x80200040
c c
stepi 10000
set confirm off set confirm off
kill kill
q q

24716
wally-pipelined/regression/wave-dos/linux-waves.do
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File diff suppressed because it is too large Load Diff

2
wally-pipelined/src/uncore/uartPC16550D.sv
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@ -269,7 +269,7 @@ module uartPC16550D(
rxdataready <= #1 1; rxdataready <= #1 1;
end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo
if (fifoenabled) begin if (fifoenabled) begin
rxfifotail <= #1 rxfifotail + 1; if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1;
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
end else rxdataready <= #1 0; end else rxdataready <= #1 0;
end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register