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Merge pull request #1193 from jordancarlin/dev

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Fix regression-wally --fcov
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David Harris 2024-12-11 22:10:47 -08:00 committed by GitHub
commit 9dbbfc4a70
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1 changed files with 4 additions and 4 deletions
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8
sim/questa/wally.do
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@ -104,10 +104,10 @@ if {[lcheck lst "--ccov"]} {
# if --fcov found set flag and remove from list
if {[lcheck lst "--fcov"]} {
set FunctCoverage 1
set FCvlog "+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \
+incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \
set FCvlog "+incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 \
+incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \
+incdir+${FCRVVI}/common +incdir+${FCRVVI}"
+incdir+${FCRVVI}/common +incdir+${FCRVVI} \
+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source"
}
# if --lockstep or --fcov found set flag and remove from list
@ -164,7 +164,7 @@ if {$DEBUG > 0} {
# because vsim will run vopt
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared"
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${FCvlog} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals