From 9d9de8f8dd2aeeefc18c873579fde867c859c094 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Feb 2023 14:39:34 -0800 Subject: [PATCH] added arch32b tests (giving errors in sim however) --- config/rv32i/wally-config.vh | 8 +- testbench/testbench.sv | 1 + testbench/tests.vh | 251 ++++++++++++++++++++++++++++++----- 3 files changed, 223 insertions(+), 37 deletions(-) diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index d400cebe9..f377468f4 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -144,10 +144,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 681d6bb9a..463ab0c46 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -131,6 +131,7 @@ logic [3:0] dummy; "embench": tests = embench; "coremark": tests = coremark; "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; + "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 5bf239ade..311a07415 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1326,10 +1326,103 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; + string arch64b[] = '{ `RISCVARCHTEST, - "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S", + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S", + "rv64i_m/I/src/add-01.S", + "rv64i_m/I/src/addi-01.S", + "rv64i_m/I/src/addiw-01.S", + "rv64i_m/I/src/addw-01.S", + "rv64i_m/I/src/and-01.S", + "rv64i_m/I/src/andi-01.S", + "rv64i_m/I/src/auipc-01.S", + "rv64i_m/I/src/beq-01.S", + "rv64i_m/I/src/bge-01.S", + "rv64i_m/I/src/bgeu-01.S", + "rv64i_m/I/src/blt-01.S", + "rv64i_m/I/src/bltu-01.S", + "rv64i_m/I/src/bne-01.S", + "rv64i_m/I/src/fence-01.S", + "rv64i_m/I/src/jal-01.S", + "rv64i_m/I/src/jalr-01.S", + "rv64i_m/I/src/lb-align-01.S", + "rv64i_m/I/src/lbu-align-01.S", + "rv64i_m/I/src/ld-align-01.S", + "rv64i_m/I/src/lh-align-01.S", + "rv64i_m/I/src/lhu-align-01.S", + "rv64i_m/I/src/lui-01.S", + "rv64i_m/I/src/lw-align-01.S", + "rv64i_m/I/src/lwu-align-01.S", + "rv64i_m/I/src/or-01.S", + "rv64i_m/I/src/ori-01.S", + "rv64i_m/I/src/sb-align-01.S", + "rv64i_m/I/src/sd-align-01.S", + "rv64i_m/I/src/sh-align-01.S", + "rv64i_m/I/src/sll-01.S", + "rv64i_m/I/src/slli-01.S", + "rv64i_m/I/src/slliw-01.S", + "rv64i_m/I/src/sllw-01.S", + "rv64i_m/I/src/slt-01.S", + "rv64i_m/I/src/slti-01.S", + "rv64i_m/I/src/sltiu-01.S", + "rv64i_m/I/src/sltu-01.S", + "rv64i_m/I/src/sra-01.S", + "rv64i_m/I/src/srai-01.S", + "rv64i_m/I/src/sraiw-01.S", + "rv64i_m/I/src/sraw-01.S", + "rv64i_m/I/src/srl-01.S", + "rv64i_m/I/src/srli-01.S", + "rv64i_m/I/src/srliw-01.S", + "rv64i_m/I/src/srlw-01.S", + "rv64i_m/I/src/sub-01.S", + "rv64i_m/I/src/subw-01.S", + "rv64i_m/I/src/sw-align-01.S", + "rv64i_m/I/src/xor-01.S", + "rv64i_m/I/src/xori-01.S", + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S" + /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bext-01.S", @@ -1339,39 +1432,131 @@ string arch64b[] = '{ "rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bseti-01.S", "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/rev8-01.S", + + + "rv64i_m/B/src/rol-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh3add.uw-01.S", - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/zext.h_64-01.S" + + + + + */ +}; + +string arch32b[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_64-01.S", + "rv32i_m/B/src/rev8-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/clzw-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/cpopw-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ctzw-01.S", + "rv32i_m/B/src/rolw-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/roriw-01.S", + "rv32i_m/B/src/rorw-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/slli.uw-01.S", + "rv32i_m/B/src/add.uw-01.S", + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S", + "rv32i_m/B/src/sh1add.uw-01.S", + "rv32i_m/B/src/sh2add.uw-01.S", + "rv32i_m/B/src/sh3add.uw-01.S", + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/addiw-01.S", + "rv32i_m/I/src/addw-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/ld-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/lwu-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sd-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slliw-01.S", + "rv32i_m/I/src/sllw-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/sraiw-01.S", + "rv32i_m/I/src/sraw-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/srliw-01.S", + "rv32i_m/I/src/srlw-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/subw-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S", + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S" + /*"rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S", + "rv64i_m/B/src/clmul-01.S", + + + + "rv64i_m/B/src/rol-01.S", + + + + + */ }; string arch32priv[] = '{ `RISCVARCHTEST,