From 9d4a3d7d05426beb659124a420734a8e88d84d70 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 May 2024 14:11:40 -0700 Subject: [PATCH] Started adding testbplan --- docs/testplans/testplan.md | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md index 37390a632..95ce72f8b 100644 --- a/docs/testplans/testplan.md +++ b/docs/testplans/testplan.md @@ -2,27 +2,22 @@ CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction. -| Functions | Coverage Method | Status | -| ----------- | ----------- |----| -| Instructions | riscv-arch-test | Pass | -| Privileged Unit | wally-riscv-arch-test | Pass | -| Virtual Memory | wally-riscv-arch-test | Pass | -| PMP | wally-riscv-arch-test | Pass -| Peripherals | wally-riscv-arch-test | Pass | -| Floating-Point | TestFloat | Pass | -| General | Code Coverage | 91% | -| General | Boot Linux in Sim | Pass | -| General | Boot Linux on FPGA | Pass | +| Tests | Section | TRL3 | TRL5 | Coverage Method | Status | Command | +| ------------------- | -------------- | ------------ | ------ | --------------------- | ------ | ------- | +| Verilator Lint | 5.3 | All configs | rv64gc | lint-wally | PASS | regression-wally --nightly | +| Instructions | 3.7 | All configs | rv64gc | riscv-arch-test | PASS | regression-wally --nightly | +| Privileged | 3.7 | All configs | rv64gc | wally-riscv-arch-test | PASS | regression-wally --nightly | +| Floating-point | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc | TestFloat | FAIL | regression-wally --nightly | +| CoreMark | 21.1 | Many configs | rv64gc | CoreMark | | regression-wally --nightly | +| Embench | 21.2 | rv32* | n/a | Embench | | regression-wally --nightly | +| Cache PV | 21.3.1 | rv{32/64}gc | rv64gc | TBD | TBD | TBD | +| Cache PV | 21.3.2 | rv{32/64}gc | rv64gc | TBD | TBD | TBD | +| Linux Boot | 22.3.2 | rv64gc | rv64gc | TBD | TBD | TBD | +| FPGA Linux Boot | 23.2 | | rv64gc | TBD | TBD | TBD | +| Code Coverage | 5.11.10 | | rv64gc | TBD | TBD | TBD | +| Functional Coverage | 5.11.11 | | rv64gc | TBD | TBD | TBD | -The following performance validation is also run: -| Function | Method | Status | -| --- | --- | --- | -| Overall Performance | embench | Pass| -| Overall Performance | coremark | Pass | -| Branch Predictor | *** | Pass | -| Cache Miss Rate | *** | Pass | - * Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.