diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index 27eaa4107..d499b1db3 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -32,33 +32,33 @@
 `include "wally-config.vh"
 
 module spill import cvw::*;  #(parameter cvw_t P) (
-  input logic              clk,               
-  input logic              reset,
-  input logic              StallD, FlushD,
+  input logic               clk,               
+  input logic               reset,
+  input logic               StallD, FlushD,
   input logic [P.XLEN-1:0]  PCF,               // 2 byte aligned PC in Fetch stage
   input logic [P.XLEN-1:2]  PCPlus4F,          // PCF + 4
   input logic [P.XLEN-1:0]  PCNextF,           // The next PCF
-  input logic [31:0]       InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
-  input logic              IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
-  input logic              ITLBMissF,         // ITLB miss, ignore memory request
-  input logic              InstrUpdateDAF,    // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
+  input logic [31:0]        InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
+  input logic               IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
+  input logic               ITLBMissF,         // ITLB miss, ignore memory request
+  input logic               InstrUpdateDAF,    // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
   output logic [P.XLEN-1:0] PCSpillNextF,      // The next PCF for one of the two memory addresses of the spill
   output logic [P.XLEN-1:0] PCSpillF,          // PCF for one of the two memory addresses of the spill
-  output logic             SelSpillNextF,     // During the transition between the two spill operations, the IFU should stall the pipeline
-  output logic [31:0]      PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
-  output logic             CompressedF);      // The fetched instruction is compressed
+  output logic              SelSpillNextF,     // During the transition between the two spill operations, the IFU should stall the pipeline
+  output logic [31:0]       PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
+  output logic              CompressedF);      // The fetched instruction is compressed
 
   // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
-  typedef enum logic [1:0]     {STATE_READY, STATE_SPILL} statetype;
-  localparam           SPILLTHRESHOLD = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/32 : 1; 
+  typedef enum logic [1:0]  {STATE_READY, STATE_SPILL} statetype;
+  localparam                SPILLTHRESHOLD = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/32 : 1; 
 
-  statetype         CurrState, NextState;
+  statetype          CurrState, NextState;
   logic [P.XLEN-1:0] PCPlus2F;         
-  logic             TakeSpillF;
-  logic             SpillF;
-  logic             SelSpillF;
-  logic             SpillSaveF;
-  logic [15:0]      InstrFirstHalfF;
+  logic              TakeSpillF;
+  logic              SpillF;
+  logic              SelSpillF;
+  logic              SpillSaveF;
+  logic [15:0]       InstrFirstHalfF;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // PC logic 
@@ -71,7 +71,6 @@ module spill import cvw::*;  #(parameter cvw_t P) (
   // select between PCF and PCF+2
   mux2 #(P.XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
 
-  
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // Detect spill
   ////////////////////////////////////////////////////////////////////////////////////////////////////