From 333e390f8d0b9c62d2f5cf59abe5a18b0f30deaf Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 13 Dec 2023 11:52:21 -0800
Subject: [PATCH 1/2] Test commit from dev

---
 src/mmu/hptw.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 64cb45f70..ab5e571c8 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -198,7 +198,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   end
 
   // Enable and select signals based on states
-  assign StartWalk  = (WalkerState == IDLE) & TLBMiss;
+  assign StartWalk  = (WalkerState == IDLE) & TLBMiss; 
   assign HPTWRW[1]  = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
   assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk;
   assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk;

From ff26baf7e82f074f8bd2218a5a3ca7c97bb484b7 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 13 Dec 2023 12:53:44 -0800
Subject: [PATCH 2/2] Rolled back attempt to support Verilator

---
 src/generic/mem/ram2p1r1wbe.sv |  4 ++--
 testbench/testbench.sv         | 40 ++++++++--------------------------
 2 files changed, 11 insertions(+), 33 deletions(-)

diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index ebc74e684..586a4e892 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -110,11 +110,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     // ***************************************************************************
     integer i;
     
-    initial begin // initialize memory for simulation only
+  /*  initial begin // initialize memory for simulation only; not needed because done in the testbench now
       integer j;
       for (j=0; j < DEPTH; j++) 
         mem[j] = '0;
-    end
+    end */
     
     // Read
     logic [$clog2(DEPTH)-1:0] ra1d;
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index c5d11b421..ece7500d5 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -86,24 +86,6 @@ module testbench;
   logic Validate;
   logic SelectTest;
 
-  // Nasty hack to get around Verilog simulators being picky about conditionally instantiated signals
-  initial begin
-    if (P.DTIM_SUPPORTED) begin
-//      `define P_DTIM_SUPPORTED=1;
-    end
-    if (P.IROM_SUPPORTED) begin
-      `define P_IROM_SUPPORTED=1;
-    end
-    if (P.BUS_SUPPORTED) begin
-      `define P_BUS_SUPPORTED=1;
-    end
-    if (P.SDC_SUPPORTED) begin
-      `define P_SDC_SUPPORTED=1;
-    end
-    if (P.UNCORE_RAM_SUPPORTED) begin
-      `define P_UNCORE_RAM_SUPPORTED=1;
-    end
-  end
 
   // pick tests based on modes supported
   initial begin
@@ -289,7 +271,7 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
     if(TestBenchReset) test = 1;
     if (TEST == "coremark")
-      if (dut.core.priv.priv.EcallFaultM) begin
+      if (dut.core.EcallFaultM) begin
         $display("Benchmark: coremark is done.");
         $stop;
       end
@@ -344,7 +326,7 @@ module testbench;
       if (P.UNCORE_RAM_SUPPORTED)
         for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
           dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
-/*    if(reset) begin  // branch predictor must always be reset
+    if(reset) begin  // branch predictor must always be reset
       if (P.BPRED_SUPPORTED) begin
         // local history only
         if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)
@@ -355,7 +337,7 @@ module testbench;
         for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
           dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
       end
-    end */
+    end
   end
 
   ////////////////////////////////////////////////////////////////////////////////
@@ -363,22 +345,18 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
   always @(posedge clk) begin
     if (LoadMem) begin
-      `ifdef P_SDC_SUPPORTED 
+      if (P.SDC_SUPPORTED) begin
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
         //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
         //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // shorten sdc timers for simulation
-        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; 
-      `elsif P_IROM_SUPPORTED   
-        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-      `else if P_BUS_SUPPORTED 
-        $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-      `endif
-      `ifdef P_DTIM_SUPPORTED
-        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-      `endif
+        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+      end 
+      else if (P.IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      if (P.DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
       $display("Read memfile %s", memfilename);
     end
   end