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https://github.com/openhwgroup/cvw
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generic cleanup
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parent
93b0286934
commit
9c79078be1
@ -28,7 +28,8 @@
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module adder #(parameter WIDTH=8) (
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module adder #(parameter WIDTH=8) (
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input logic [WIDTH-1:0] a, b,
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input logic [WIDTH-1:0] a, b,
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output logic [WIDTH-1:0] y);
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output logic [WIDTH-1:0] y
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);
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assign y = a + b;
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assign y = a + b;
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endmodule
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endmodule
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@ -28,7 +28,8 @@
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module aplusbeq0 #(parameter WIDTH = 8) (
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module aplusbeq0 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] a, b,
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input logic [WIDTH-1:0] a, b,
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output logic zero);
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output logic zero
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);
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logic [WIDTH-1:0] x;
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logic [WIDTH-1:0] x;
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logic [WIDTH-1:0] orshift;
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logic [WIDTH-1:0] orshift;
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@ -29,16 +29,17 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module arrs
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module arrs(
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(input logic clk,
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input logic clk,
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input logic areset,
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input logic areset,
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output logic reset);
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output logic reset
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);
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logic metaStable;
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logic metaStable;
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logic resetB;
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logic resetB;
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always_ff @(posedge clk , posedge areset) begin
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always_ff @(posedge clk , posedge areset) begin
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if(areset) begin
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if (areset) begin
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metaStable <= 1'b0;
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metaStable <= 1'b0;
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resetB <= 1'b0;
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resetB <= 1'b0;
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end else begin
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end else begin
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@ -48,5 +49,4 @@ module arrs
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end
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end
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assign reset = ~resetB;
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assign reset = ~resetB;
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endmodule
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// prioritythermometer.sv
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// binencoder.sv
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//
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//
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// Written: ross1728@gmail.com November 14, 2022
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// Written: ross1728@gmail.com November 14, 2022
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//
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//
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@ -23,10 +23,15 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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module binencoder #(parameter N = 8) (
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module binencoder #(parameter N = 8) (
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input logic [N-1:0] A,
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input logic [N-1:0] A, // one-hot input
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output logic [$clog2(N)-1:0] Y);
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output logic [$clog2(N)-1:0] Y // binary-encoded output
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);
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integer index;
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integer index;
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// behavioral description
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// this is coded as a priority encoder
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// consider redesigning to take advanteage of one-hot nature of input
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always_comb begin
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always_comb begin
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Y = 0;
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Y = 0;
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for(index = 0; index < N; index++)
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for(index = 0; index < N; index++)
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@ -26,21 +26,15 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module clockgater
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module clockgater (
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(input logic E,
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input logic E,
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input logic SE,
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input logic SE,
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input logic CLK,
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input logic CLK,
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output logic ECLK);
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output logic ECLK
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);
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if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
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else begin
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if (`FPGA) begin
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BUFGCE bufgce_i0 (
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.I(CLK),
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.CE(E | SE),
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.O(ECLK)
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);
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end else begin
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// *** BUG
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// *** BUG
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// VERY IMPORTANT.
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// VERY IMPORTANT.
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// This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
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// This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
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@ -48,7 +42,7 @@ module clockgater
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logic enable_q;
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logic enable_q;
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always_latch begin
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always_latch begin
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if(~CLK) begin
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if(~CLK) begin
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enable_q <= E | SE;
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enable_q <= E | SE;
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end
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end
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end
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end
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assign ECLK = enable_q & CLK;
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assign ECLK = enable_q & CLK;
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@ -28,7 +28,8 @@
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module counter #(parameter WIDTH=8) (
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module counter #(parameter WIDTH=8) (
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input logic clk, reset, en,
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input logic clk, reset, en,
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output logic [WIDTH-1:0] q);
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output logic [WIDTH-1:0] q
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);
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logic [WIDTH-1:0] qnext;
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logic [WIDTH-1:0] qnext;
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@ -36,6 +36,5 @@ module csa #(parameter N=16) (
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// s + c = x + y + z + cin
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// s + c = x + y + z + cin
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assign s = x ^ y ^ z;
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assign s = x ^ y ^ z;
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assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) |
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assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) | (y[N-2:0] & z[N-2:0]), cin};
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(y[N-2:0] & z[N-2:0]), cin};
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endmodule
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endmodule
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@ -26,7 +26,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module decoder #(parameter BINARY_BITS = 3) (
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module decoder #(parameter BINARY_BITS = 3) (
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input logic [BINARY_BITS-1:0] binary,
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input logic [BINARY_BITS-1:0] binary,
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output logic [(2**BINARY_BITS)-1:0] onehot
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output logic [(2**BINARY_BITS)-1:0] onehot
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);
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);
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@ -23,20 +23,16 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//leading zero counter i.e. priority encoder
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module lzc #(parameter WIDTH = 1) (
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module lzc #(parameter WIDTH = 1) (
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input logic [WIDTH-1:0] num, // number to count the leading zeroes of
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input logic [WIDTH-1:0] num, // number to count the leading zeroes of
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output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes
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output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes
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);
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);
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/* verilator lint_off CMPCONST */
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/* verilator lint_off WIDTH */
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integer i;
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logic [31:0] i;
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always_comb begin
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always_comb begin
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i = 0;
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i = 0;
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while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one
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while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one
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ZeroCnt = i[$clog2(WIDTH)-1:0];
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ZeroCnt = i;
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end
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end
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/* verilator lint_on WIDTH */
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/* verilator lint_on CMPCONST */
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endmodule
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endmodule
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`include "wally-config.vh"
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`include "wally-config.vh"
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module onehotdecoder
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module onehotdecoder #(parameter WIDTH = 2) (
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#(parameter WIDTH = 2)
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input logic [WIDTH-1:0] bin,
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(input logic [WIDTH-1:0] bin,
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output logic [2**WIDTH-1:0] decoded
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output logic [2**WIDTH-1:0] decoded
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);
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);
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always_comb begin
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always_comb begin
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decoded = '0;
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decoded = '0;
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@ -4,7 +4,7 @@
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// Written: David_Harris@hmc.edu 13 July 2021
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// Written: David_Harris@hmc.edu 13 July 2021
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// Modified:
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// Modified:
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//
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//
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// Purpose: Various flavors of multiplexers
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// Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs
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//
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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//
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@ -25,26 +25,28 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`include "wally-config.vh"
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/* verilator lint_off DECLFILENAME */
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/* verilator lint_off UNOPTFLAT */
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// perform an OR of all the rows in an array, producing one output for each column
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// perform an OR of all the rows in an array, producing one output for each column
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// equivalent to assign y = a.or
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// equivalent to assign y = a.or
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module or_rows #(parameter ROWS = 8, COLS=2) (
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module or_rows #(parameter ROWS = 8, COLS=2) (
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input var logic [COLS-1:0] a[ROWS-1:0],
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input var logic [COLS-1:0] a[ROWS-1:0],
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output logic [COLS-1:0] y);
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output logic [COLS-1:0] y
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);
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genvar row;
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genvar row;
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if(ROWS == 1)
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if(ROWS == 1)
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assign y = a[0];
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assign y = a[0];
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else begin
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else begin
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/* verilator lint_off UNOPTFLAT */
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logic [COLS-1:0] mid[ROWS-1:1];
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logic [COLS-1:0] mid[ROWS-1:1];
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assign mid[1] = a[0] | a[1];
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assign mid[1] = a[0] | a[1];
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for (row=2; row < ROWS; row++)
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for (row=2; row < ROWS; row++)
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assign mid[row] = mid[row-1] | a[row];
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assign mid[row] = mid[row-1] | a[row];
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assign y = mid[ROWS-1];
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assign y = mid[ROWS-1];
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/* verilator lint_on UNOPTFLAT */
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end
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end
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endmodule
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endmodule
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/* verilator lint_on UNOPTFLAT */
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/* verilator lint_on DECLFILENAME */
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@ -4,8 +4,10 @@
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// Written: David_Harris@hmc.edu 9 January 2021
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// Modified:
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//
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//
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// Purpose: Determine forwarding, stalls and flushes
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// Purpose: Determine stalls and flushes
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//
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//
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// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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@ -28,21 +30,21 @@
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module hazard(
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module hazard(
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// Detect hazards
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// Detect hazards
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(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
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(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
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(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
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(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
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(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
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(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
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(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD,
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(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD,
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(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
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(* mark_debug = "true" *) input logic DivBusyE, FDivBusyE,
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(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
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(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
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(* mark_debug = "true" *) input logic WFIStallM,
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(* mark_debug = "true" *) input logic WFIStallM,
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// Stall & flush outputs
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// Stall & flush outputs
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(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
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(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
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(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
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(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
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);
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);
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logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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logic FlushDCause, FlushECause, FlushMCause, FlushWCause;
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logic FlushDCause, FlushECause, FlushMCause, FlushWCause;
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// stalls and flushes
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// stalls and flushes
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// loads: stall for one cycle if the subsequent instruction depends on the load
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// loads: stall for one cycle if the subsequent instruction depends on the load
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@ -92,6 +94,7 @@ module hazard(
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assign #1 StallM = StallMCause | StallW;
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assign #1 StallM = StallMCause | StallW;
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assign #1 StallW = StallWCause;
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assign #1 StallW = StallWCause;
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// detect the first stage that is not stalled
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assign FirstUnstalledD = ~StallD & StallF;
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assign FirstUnstalledD = ~StallD & StallF;
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assign FirstUnstalledE = ~StallE & StallD;
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assign FirstUnstalledE = ~StallE & StallD;
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assign FirstUnstalledM = ~StallM & StallE;
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assign FirstUnstalledM = ~StallM & StallE;
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