generic cleanup

This commit is contained in:
David Harris 2023-01-14 18:56:46 -08:00
parent 93b0286934
commit 9c79078be1
12 changed files with 66 additions and 65 deletions

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@ -28,7 +28,8 @@
module adder #(parameter WIDTH=8) ( module adder #(parameter WIDTH=8) (
input logic [WIDTH-1:0] a, b, input logic [WIDTH-1:0] a, b,
output logic [WIDTH-1:0] y); output logic [WIDTH-1:0] y
);
assign y = a + b; assign y = a + b;
endmodule endmodule

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@ -28,7 +28,8 @@
module aplusbeq0 #(parameter WIDTH = 8) ( module aplusbeq0 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a, b, input logic [WIDTH-1:0] a, b,
output logic zero); output logic zero
);
logic [WIDTH-1:0] x; logic [WIDTH-1:0] x;
logic [WIDTH-1:0] orshift; logic [WIDTH-1:0] orshift;

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@ -29,16 +29,17 @@
`include "wally-config.vh" `include "wally-config.vh"
module arrs module arrs(
(input logic clk, input logic clk,
input logic areset, input logic areset,
output logic reset); output logic reset
);
logic metaStable; logic metaStable;
logic resetB; logic resetB;
always_ff @(posedge clk , posedge areset) begin always_ff @(posedge clk , posedge areset) begin
if(areset) begin if (areset) begin
metaStable <= 1'b0; metaStable <= 1'b0;
resetB <= 1'b0; resetB <= 1'b0;
end else begin end else begin
@ -48,5 +49,4 @@ module arrs
end end
assign reset = ~resetB; assign reset = ~resetB;
endmodule endmodule

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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// prioritythermometer.sv // binencoder.sv
// //
// Written: ross1728@gmail.com November 14, 2022 // Written: ross1728@gmail.com November 14, 2022
// //
@ -23,10 +23,15 @@
/////////////////////////////////////////// ///////////////////////////////////////////
module binencoder #(parameter N = 8) ( module binencoder #(parameter N = 8) (
input logic [N-1:0] A, input logic [N-1:0] A, // one-hot input
output logic [$clog2(N)-1:0] Y); output logic [$clog2(N)-1:0] Y // binary-encoded output
);
integer index; integer index;
// behavioral description
// this is coded as a priority encoder
// consider redesigning to take advanteage of one-hot nature of input
always_comb begin always_comb begin
Y = 0; Y = 0;
for(index = 0; index < N; index++) for(index = 0; index < N; index++)

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@ -26,21 +26,15 @@
`include "wally-config.vh" `include "wally-config.vh"
module clockgater module clockgater (
(input logic E, input logic E,
input logic SE, input logic SE,
input logic CLK, input logic CLK,
output logic ECLK); output logic ECLK
);
if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
else begin
if (`FPGA) begin
BUFGCE bufgce_i0 (
.I(CLK),
.CE(E | SE),
.O(ECLK)
);
end else begin
// *** BUG // *** BUG
// VERY IMPORTANT. // VERY IMPORTANT.
// This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would. // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
@ -48,7 +42,7 @@ module clockgater
logic enable_q; logic enable_q;
always_latch begin always_latch begin
if(~CLK) begin if(~CLK) begin
enable_q <= E | SE; enable_q <= E | SE;
end end
end end
assign ECLK = enable_q & CLK; assign ECLK = enable_q & CLK;

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@ -28,7 +28,8 @@
module counter #(parameter WIDTH=8) ( module counter #(parameter WIDTH=8) (
input logic clk, reset, en, input logic clk, reset, en,
output logic [WIDTH-1:0] q); output logic [WIDTH-1:0] q
);
logic [WIDTH-1:0] qnext; logic [WIDTH-1:0] qnext;

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@ -36,6 +36,5 @@ module csa #(parameter N=16) (
// s + c = x + y + z + cin // s + c = x + y + z + cin
assign s = x ^ y ^ z; assign s = x ^ y ^ z;
assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) | assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) | (y[N-2:0] & z[N-2:0]), cin};
(y[N-2:0] & z[N-2:0]), cin};
endmodule endmodule

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@ -26,7 +26,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module decoder #(parameter BINARY_BITS = 3) ( module decoder #(parameter BINARY_BITS = 3) (
input logic [BINARY_BITS-1:0] binary, input logic [BINARY_BITS-1:0] binary,
output logic [(2**BINARY_BITS)-1:0] onehot output logic [(2**BINARY_BITS)-1:0] onehot
); );

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@ -23,20 +23,16 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
//leading zero counter i.e. priority encoder
module lzc #(parameter WIDTH = 1) ( module lzc #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] num, // number to count the leading zeroes of input logic [WIDTH-1:0] num, // number to count the leading zeroes of
output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes
); );
/* verilator lint_off CMPCONST */
/* verilator lint_off WIDTH */ integer i;
logic [31:0] i; always_comb begin
always_comb begin i = 0;
i = 0; while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one
while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one ZeroCnt = i[$clog2(WIDTH)-1:0];
ZeroCnt = i; end
end
/* verilator lint_on WIDTH */
/* verilator lint_on CMPCONST */
endmodule endmodule

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@ -26,11 +26,10 @@
`include "wally-config.vh" `include "wally-config.vh"
module onehotdecoder module onehotdecoder #(parameter WIDTH = 2) (
#(parameter WIDTH = 2) input logic [WIDTH-1:0] bin,
(input logic [WIDTH-1:0] bin, output logic [2**WIDTH-1:0] decoded
output logic [2**WIDTH-1:0] decoded );
);
always_comb begin always_comb begin
decoded = '0; decoded = '0;

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@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 13 July 2021 // Written: David_Harris@hmc.edu 13 July 2021
// Modified: // Modified:
// //
// Purpose: Various flavors of multiplexers // Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs
// //
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
@ -25,26 +25,28 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_off DECLFILENAME */
/* verilator lint_off UNOPTFLAT */
// perform an OR of all the rows in an array, producing one output for each column // perform an OR of all the rows in an array, producing one output for each column
// equivalent to assign y = a.or // equivalent to assign y = a.or
module or_rows #(parameter ROWS = 8, COLS=2) ( module or_rows #(parameter ROWS = 8, COLS=2) (
input var logic [COLS-1:0] a[ROWS-1:0], input var logic [COLS-1:0] a[ROWS-1:0],
output logic [COLS-1:0] y); output logic [COLS-1:0] y
);
genvar row; genvar row;
if(ROWS == 1) if(ROWS == 1)
assign y = a[0]; assign y = a[0];
else begin else begin
/* verilator lint_off UNOPTFLAT */
logic [COLS-1:0] mid[ROWS-1:1]; logic [COLS-1:0] mid[ROWS-1:1];
assign mid[1] = a[0] | a[1]; assign mid[1] = a[0] | a[1];
for (row=2; row < ROWS; row++) for (row=2; row < ROWS; row++)
assign mid[row] = mid[row-1] | a[row]; assign mid[row] = mid[row-1] | a[row];
assign y = mid[ROWS-1]; assign y = mid[ROWS-1];
/* verilator lint_on UNOPTFLAT */
end end
endmodule endmodule
/* verilator lint_on UNOPTFLAT */
/* verilator lint_on DECLFILENAME */

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@ -4,8 +4,10 @@
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu 9 January 2021
// Modified: // Modified:
// //
// Purpose: Determine forwarding, stalls and flushes // Purpose: Determine stalls and flushes
// //
// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -28,21 +30,21 @@
module hazard( module hazard(
// Detect hazards // Detect hazards
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM, (* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM,
(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, (* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
(* mark_debug = "true" *) input logic LSUStallM, IFUStallF, (* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD, (* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD,
(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE, (* mark_debug = "true" *) input logic DivBusyE, FDivBusyE,
(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM, (* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
(* mark_debug = "true" *) input logic WFIStallM, (* mark_debug = "true" *) input logic WFIStallM,
// Stall & flush outputs // Stall & flush outputs
(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, (* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW (* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW
); );
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW; logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
logic FlushDCause, FlushECause, FlushMCause, FlushWCause; logic FlushDCause, FlushECause, FlushMCause, FlushWCause;
// stalls and flushes // stalls and flushes
// loads: stall for one cycle if the subsequent instruction depends on the load // loads: stall for one cycle if the subsequent instruction depends on the load
@ -92,6 +94,7 @@ module hazard(
assign #1 StallM = StallMCause | StallW; assign #1 StallM = StallMCause | StallW;
assign #1 StallW = StallWCause; assign #1 StallW = StallWCause;
// detect the first stage that is not stalled
assign FirstUnstalledD = ~StallD & StallF; assign FirstUnstalledD = ~StallD & StallF;
assign FirstUnstalledE = ~StallE & StallD; assign FirstUnstalledE = ~StallE & StallD;
assign FirstUnstalledM = ~StallM & StallE; assign FirstUnstalledM = ~StallM & StallE;