From c9b56f9acca5bc07cf205cda4dd24662e49a5559 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 05:06:56 -0800
Subject: [PATCH 01/13] Only add memory libraries when targeting 28nm

---
 synthDC/.synopsys_dc.setup | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 8b0ba0309..492256568 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -48,10 +48,12 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-set memory /home/jstine/WallyMem/rv64gc/
-lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
-lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
-lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+if {$tech="tsmc28"} {}
+    set memory /home/jstine/WallyMem/rv64gc/
+    lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
+    lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
+    lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+}
 
 # Set up User Information
 set company "Oklahoma State University"

From 129380db0bdc833046ebbef9c8072285c51ed771 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 05:49:30 -0800
Subject: [PATCH 02/13] Fixed typo in DC setup for memories

---
 synthDC/.synopsys_dc.setup | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 492256568..2fdc11c27 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -48,7 +48,7 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-if {$tech="tsmc28"} {}
+if {$tech == "tsmc28"} {
     set memory /home/jstine/WallyMem/rv64gc/
     lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
     lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db

From 93f57402df76f4acbb88446e14889f76bfdc4f59 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 15:43:52 -0800
Subject: [PATCH 03/13] Removed O2 from fir Makefile to be consistent with lab.

---
 examples/C/fir/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile
index c27e423a5..4e3991e46 100644
--- a/examples/C/fir/Makefile
+++ b/examples/C/fir/Makefile
@@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET)
 	spike $(TARGET)
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\
+	riscv64-unknown-elf-gcc -o $(TARGET) -g\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \

From 99d179dd3e37072dfc17cb59d44655c873abe0b1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 14:14:11 -0800
Subject: [PATCH 04/13] Removed pipelined level of hierarchy

---
 .gitignore                                    | 23 ++++++++-----------
 Install                                       |  2 +-
 Makefile                                      |  4 ++--
 README.md                                     |  2 +-
 benchmarks/coremark/Makefile                  |  2 +-
 benchmarks/embench/Makefile                   |  2 +-
 .../buildroot/wally-config.vh                 |  0
 .../config => config}/fpga/wally-config.vh    |  0
 .../config => config}/rv32e/wally-config.vh   |  0
 .../config => config}/rv32gc/wally-config.vh  |  0
 .../config => config}/rv32i/wally-config.vh   |  0
 .../config => config}/rv32imc/wally-config.vh |  0
 .../rv64fpquad/wally-config.vh                |  0
 .../config => config}/rv64gc/wally-config.vh  |  0
 .../config => config}/rv64i/wally-config.vh   |  0
 {pipelined/config => config}/shared/README    |  0
 .../config => config}/shared/wally-shared.vh  |  0
 fpga/README.md                                |  2 +-
 fpga/generator/Makefile                       |  2 +-
 fpga/generator/wally.tcl                      |  2 +-
 {pipelined/regression => regression}/Makefile |  0
 .../buildrootBugFinder.py                     |  0
 .../regression => regression}/fpga-wave.do    |  0
 .../regression => regression}/imperas.ic      |  0
 .../regression => regression}/lint-wally      |  0
 .../regression => regression}/linux-wave.do   |  0
 .../regression => regression}/make-tests.sh   |  2 +-
 .../makefile-memfile                          |  0
 .../regression-wally                          |  0
 .../run-imperasdv-tests.bash                  |  0
 .../regression => regression}/sim-buildroot   |  0
 .../sim-buildroot-batch                       |  0
 .../regression => regression}/sim-imperas     |  0
 .../regression => regression}/sim-testfloat   |  0
 .../sim-testfloat-batch                       |  0
 .../regression => regression}/sim-wally       |  0
 .../regression => regression}/sim-wally-batch |  0
 .../slack-notifier/slack-notifier.py          |  0
 {pipelined/regression => regression}/test     |  0
 .../regression => regression}/testfloat.do    |  0
 .../wally-pipelined-batch.do                  |  0
 .../wally-pipelined-imperas-no-idv.do         |  0
 .../wally-pipelined-imperas.do                |  0
 .../wally-pipelined.do                        |  0
 .../regression => regression}/wave-all.do     |  0
 .../wave-dos/ahb-muldiv.do                    |  0
 .../wave-dos/ahb-waves.do                     |  0
 .../wave-dos/cache-waves.do                   |  0
 .../wave-dos/default-waves.do                 |  0
 .../wave-dos/generic.do                       |  0
 .../wave-dos/linux-waves.do                   |  0
 .../wave-dos/peripheral-waves.do              |  0
 .../regression => regression}/wave-fpu.do     |  0
 {pipelined/regression => regression}/wave.do  |  0
 setup.imperas.sh                              |  2 +-
 {pipelined/src => src}/cache/cache.sv         |  0
 {pipelined/src => src}/cache/cacheLRU.sv      |  0
 {pipelined/src => src}/cache/cachefsm.sv      |  0
 {pipelined/src => src}/cache/cacheway.sv      |  0
 .../src => src}/cache/subcachelineread.sv     |  0
 .../src => src}/ebu/ahbcacheinterface.sv      |  0
 {pipelined/src => src}/ebu/ahbinterface.sv    |  0
 {pipelined/src => src}/ebu/buscachefsm.sv     |  0
 {pipelined/src => src}/ebu/busfsm.sv          |  0
 .../src => src}/ebu/controllerinputstage.sv   |  0
 {pipelined/src => src}/ebu/ebu.sv             |  0
 {pipelined/src => src}/ebu/ebuarbfsm.sv       |  0
 {pipelined/src => src}/fpu/fclassify.sv       |  0
 {pipelined/src => src}/fpu/fcmp.sv            |  0
 {pipelined/src => src}/fpu/fctrl.sv           |  0
 {pipelined/src => src}/fpu/fcvt.sv            |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrt.sv      |  0
 .../fpu/fdivsqrt/fdivsqrtexpcalc.sv           |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfgen2.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfgen4.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfsm.sv   |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtiter.sv  |  0
 .../fpu/fdivsqrt/fdivsqrtpostproc.sv          |  0
 .../fpu/fdivsqrt/fdivsqrtpreproc.sv           |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtqsel2.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtqsel4.sv |  0
 .../fpu/fdivsqrt/fdivsqrtqsel4cmp.sv          |  0
 .../fpu/fdivsqrt/fdivsqrtstage2.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtstage4.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtuotfc2.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtuotfc4.sv            |  0
 {pipelined/src => src}/fpu/fhazard.sv         |  0
 {pipelined/src => src}/fpu/fma/fma.sv         |  0
 {pipelined/src => src}/fpu/fma/fmaadd.sv      |  0
 {pipelined/src => src}/fpu/fma/fmaalign.sv    |  0
 {pipelined/src => src}/fpu/fma/fmaexpadd.sv   |  0
 {pipelined/src => src}/fpu/fma/fmalza.sv      |  0
 {pipelined/src => src}/fpu/fma/fmamult.sv     |  0
 {pipelined/src => src}/fpu/fma/fmasign.sv     |  0
 {pipelined/src => src}/fpu/fpu.sv             |  0
 {pipelined/src => src}/fpu/fregfile.sv        |  0
 {pipelined/src => src}/fpu/fsgninj.sv         |  0
 .../src => src}/fpu/postproc/cvtshiftcalc.sv  |  0
 .../src => src}/fpu/postproc/divshiftcalc.sv  |  0
 {pipelined/src => src}/fpu/postproc/flags.sv  |  0
 .../src => src}/fpu/postproc/fmashiftcalc.sv  |  0
 .../src => src}/fpu/postproc/negateintres.sv  |  0
 .../src => src}/fpu/postproc/normshift.sv     |  0
 .../src => src}/fpu/postproc/postprocess.sv   |  0
 .../src => src}/fpu/postproc/resultsign.sv    |  0
 {pipelined/src => src}/fpu/postproc/round.sv  |  0
 .../src => src}/fpu/postproc/roundsign.sv     |  0
 .../fpu/postproc/shiftcorrection.sv           |  0
 .../src => src}/fpu/postproc/specialcase.sv   |  0
 {pipelined/src => src}/fpu/unpack.sv          |  0
 {pipelined/src => src}/fpu/unpackinput.sv     |  0
 {pipelined/src => src}/generic/adder.sv       |  0
 {pipelined/src => src}/generic/aplusbeq0.sv   |  0
 {pipelined/src => src}/generic/arrs.sv        |  0
 {pipelined/src => src}/generic/binencoder.sv  |  0
 {pipelined/src => src}/generic/clockgater.sv  |  0
 {pipelined/src => src}/generic/counter.sv     |  0
 {pipelined/src => src}/generic/csa.sv         |  0
 {pipelined/src => src}/generic/decoder.sv     |  0
 {pipelined/src => src}/generic/flop/flop.sv   |  0
 {pipelined/src => src}/generic/flop/flopen.sv |  0
 .../src => src}/generic/flop/flopenl.sv       |  0
 .../src => src}/generic/flop/flopenr.sv       |  0
 .../src => src}/generic/flop/flopenrc.sv      |  0
 .../src => src}/generic/flop/flopens.sv       |  0
 {pipelined/src => src}/generic/flop/flopr.sv  |  0
 {pipelined/src => src}/generic/flop/floprc.sv |  0
 .../src => src}/generic/flop/synchronizer.sv  |  0
 {pipelined/src => src}/generic/lzc.sv         |  0
 .../src => src}/generic/mem/ram1p1rwbe.sv     |  0
 .../generic/mem/ram1p1rwbe_64x128.sv          |  0
 .../generic/mem/ram1p1rwbe_64x44.sv           |  0
 .../src => src}/generic/mem/ram2p1r1wbe.sv    |  0
 .../generic/mem/ram2p1r1wbe_1024x68.sv        |  0
 .../generic/mem/ram2p1r1wbe_64x32.sv          |  0
 {pipelined/src => src}/generic/mem/rom1p1r.sv |  0
 .../src => src}/generic/mem/rom1p1r_128x32.sv |  0
 .../src => src}/generic/mem/rom1p1r_128x64.sv |  0
 {pipelined/src => src}/generic/mux.sv         |  0
 {pipelined/src => src}/generic/neg.sv         |  0
 .../src => src}/generic/onehotdecoder.sv      |  0
 {pipelined/src => src}/generic/or_rows.sv     |  0
 .../src => src}/generic/priorityonehot.sv     |  0
 .../generic/prioritythermometer.sv            |  0
 {pipelined/src => src}/hazard/hazard.sv       |  0
 {pipelined/src => src}/ieu/alu.sv             |  0
 {pipelined/src => src}/ieu/comparator.sv      |  0
 {pipelined/src => src}/ieu/controller.sv      |  0
 {pipelined/src => src}/ieu/datapath.sv        |  0
 {pipelined/src => src}/ieu/extend.sv          |  0
 {pipelined/src => src}/ieu/forward.sv         |  0
 {pipelined/src => src}/ieu/ieu.sv             |  0
 {pipelined/src => src}/ieu/regfile.sv         |  0
 {pipelined/src => src}/ieu/shifter.sv         |  0
 {pipelined/src => src}/ifu/CodeAligner.py     |  0
 .../src => src}/ifu/bpred/RASPredictor.sv     |  0
 {pipelined/src => src}/ifu/bpred/bpred.sv     |  0
 {pipelined/src => src}/ifu/bpred/btb.sv       |  0
 .../src => src}/ifu/bpred/foldedgshare.sv     |  0
 .../src => src}/ifu/bpred/globalhistory.sv    |  0
 {pipelined/src => src}/ifu/bpred/gshare.sv    |  0
 .../ifu/bpred/localHistoryPredictor.sv        |  0
 {pipelined/src => src}/ifu/bpred/optgshare.sv |  0
 .../src => src}/ifu/bpred/satCounter2.sv      |  0
 .../ifu/bpred/speculativeglobalhistory.sv     |  0
 .../ifu/bpred/speculativegshare.sv            |  0
 .../src => src}/ifu/bpred/twoBitPredictor.sv  |  0
 {pipelined/src => src}/ifu/decompress.sv      |  0
 {pipelined/src => src}/ifu/ifu.sv             |  0
 {pipelined/src => src}/ifu/irom.sv            |  0
 {pipelined/src => src}/ifu/spill.sv           |  0
 {pipelined/src => src}/lsu/amoalu.sv          |  0
 {pipelined/src => src}/lsu/atomic.sv          |  0
 {pipelined/src => src}/lsu/dtim.sv            |  0
 {pipelined/src => src}/lsu/endianswap.sv      |  0
 {pipelined/src => src}/lsu/lrsc.sv            |  0
 {pipelined/src => src}/lsu/lsu.sv             |  0
 {pipelined/src => src}/lsu/subwordread.sv     |  0
 {pipelined/src => src}/lsu/subwordwrite.sv    |  0
 {pipelined/src => src}/lsu/swbytemask.sv      |  0
 {pipelined/src => src}/mdu/intdivrestoring.sv |  0
 .../src => src}/mdu/intdivrestoringstep.sv    |  0
 {pipelined/src => src}/mdu/mdu.sv             |  0
 {pipelined/src => src}/mdu/mul.sv             |  0
 {pipelined/src => src}/mmu/adrdec.sv          |  0
 {pipelined/src => src}/mmu/adrdecs.sv         |  0
 {pipelined/src => src}/mmu/hptw.sv            |  0
 {pipelined/src => src}/mmu/mmu.sv             |  0
 {pipelined/src => src}/mmu/pmachecker.sv      |  0
 {pipelined/src => src}/mmu/pmpadrdec.sv       |  0
 {pipelined/src => src}/mmu/pmpchecker.sv      |  0
 {pipelined/src => src}/mmu/tlb.sv             |  0
 {pipelined/src => src}/mmu/tlbcam.sv          |  0
 {pipelined/src => src}/mmu/tlbcamline.sv      |  0
 {pipelined/src => src}/mmu/tlbcontrol.sv      |  0
 {pipelined/src => src}/mmu/tlblru.sv          |  0
 {pipelined/src => src}/mmu/tlbmixer.sv        |  0
 {pipelined/src => src}/mmu/tlbram.sv          |  0
 {pipelined/src => src}/mmu/tlbramline.sv      |  0
 {pipelined/src => src}/mmu/vm64check.sv       |  0
 {pipelined/src => src}/privileged/csr.sv      |  0
 {pipelined/src => src}/privileged/csrc.sv     |  0
 {pipelined/src => src}/privileged/csri.sv     |  0
 {pipelined/src => src}/privileged/csrm.sv     |  0
 {pipelined/src => src}/privileged/csrs.sv     |  0
 {pipelined/src => src}/privileged/csrsr.sv    |  0
 {pipelined/src => src}/privileged/csru.sv     |  0
 {pipelined/src => src}/privileged/privdec.sv  |  0
 .../src => src}/privileged/privileged.sv      |  0
 {pipelined/src => src}/privileged/privmode.sv |  0
 .../src => src}/privileged/privpiperegs.sv    |  0
 {pipelined/src => src}/privileged/trap.sv     |  0
 {pipelined/src => src}/uncore/ahbapbbridge.sv |  0
 {pipelined/src => src}/uncore/clint_apb.sv    |  0
 {pipelined/src => src}/uncore/gpio_apb.sv     |  0
 {pipelined/src => src}/uncore/plic_apb.sv     |  0
 {pipelined/src => src}/uncore/ram_ahb.sv      |  0
 {pipelined/src => src}/uncore/rom_ahb.sv      |  0
 {pipelined/src => src}/uncore/uartPC16550D.sv |  0
 {pipelined/src => src}/uncore/uart_apb.sv     |  0
 {pipelined/src => src}/uncore/uncore.sv       |  0
 {pipelined/src => src}/wally/cvw.sv           |  0
 .../src => src}/wally/wallypipelinedcore.sv   |  0
 .../src => src}/wally/wallypipelinedsoc.sv    |  0
 synthDC/Makefile                              |  6 ++---
 synthDC/scripts/synth.tcl                     |  2 +-
 .../common/functionName.sv                    |  0
 .../common/instrNameDecTB.sv                  |  0
 .../common/instrTrackerTB.sv                  |  0
 .../common/wallyTracer.sv                     |  0
 {pipelined/testbench => testbench}/fp/case.sh |  0
 .../testbench => testbench}/sdc/ram2sdLoad.py |  0
 .../testbench => testbench}/sdc/ramdisk2.hex  |  0
 .../testbench => testbench}/sdc/run_tb.do     |  0
 .../testbench => testbench}/sdc/sdModel.sv    |  0
 .../testbench => testbench}/sdc/sd_crc_16.sv  |  0
 .../testbench => testbench}/sdc/sd_crc_7.sv   |  0
 .../testbench => testbench}/sdc/sd_defines.h  |  0
 .../testbench => testbench}/sdc/sd_top_tb.sv  |  0
 .../testbench => testbench}/sdc/wave.do       |  0
 .../testbench => testbench}/testbench-fp.sv   |  2 +-
 .../testbench-linux.sv                        |  0
 .../testbench => testbench}/testbench.sv      |  2 +-
 .../testbench_imperas.sv                      |  0
 .../testbench => testbench}/tests-fp.vh       |  0
 {pipelined/testbench => testbench}/tests.vh   | 14 +++++------
 tests/testgen/privileged/run.sh               |  4 ++--
 247 files changed, 35 insertions(+), 40 deletions(-)
 rename {pipelined/config => config}/buildroot/wally-config.vh (100%)
 rename {pipelined/config => config}/fpga/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32e/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32gc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32i/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32imc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64fpquad/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64gc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64i/wally-config.vh (100%)
 rename {pipelined/config => config}/shared/README (100%)
 rename {pipelined/config => config}/shared/wally-shared.vh (100%)
 rename {pipelined/regression => regression}/Makefile (100%)
 rename {pipelined/regression => regression}/buildrootBugFinder.py (100%)
 rename {pipelined/regression => regression}/fpga-wave.do (100%)
 rename {pipelined/regression => regression}/imperas.ic (100%)
 rename {pipelined/regression => regression}/lint-wally (100%)
 rename {pipelined/regression => regression}/linux-wave.do (100%)
 rename {pipelined/regression => regression}/make-tests.sh (88%)
 rename {pipelined/regression => regression}/makefile-memfile (100%)
 rename {pipelined/regression => regression}/regression-wally (100%)
 rename {pipelined/regression => regression}/run-imperasdv-tests.bash (100%)
 rename {pipelined/regression => regression}/sim-buildroot (100%)
 rename {pipelined/regression => regression}/sim-buildroot-batch (100%)
 rename {pipelined/regression => regression}/sim-imperas (100%)
 rename {pipelined/regression => regression}/sim-testfloat (100%)
 rename {pipelined/regression => regression}/sim-testfloat-batch (100%)
 rename {pipelined/regression => regression}/sim-wally (100%)
 rename {pipelined/regression => regression}/sim-wally-batch (100%)
 rename {pipelined/regression => regression}/slack-notifier/slack-notifier.py (100%)
 rename {pipelined/regression => regression}/test (100%)
 rename {pipelined/regression => regression}/testfloat.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-batch.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-imperas-no-idv.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-imperas.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined.do (100%)
 rename {pipelined/regression => regression}/wave-all.do (100%)
 rename {pipelined/regression => regression}/wave-dos/ahb-muldiv.do (100%)
 rename {pipelined/regression => regression}/wave-dos/ahb-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/cache-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/default-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/generic.do (100%)
 rename {pipelined/regression => regression}/wave-dos/linux-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/peripheral-waves.do (100%)
 rename {pipelined/regression => regression}/wave-fpu.do (100%)
 rename {pipelined/regression => regression}/wave.do (100%)
 rename {pipelined/src => src}/cache/cache.sv (100%)
 rename {pipelined/src => src}/cache/cacheLRU.sv (100%)
 rename {pipelined/src => src}/cache/cachefsm.sv (100%)
 rename {pipelined/src => src}/cache/cacheway.sv (100%)
 rename {pipelined/src => src}/cache/subcachelineread.sv (100%)
 rename {pipelined/src => src}/ebu/ahbcacheinterface.sv (100%)
 rename {pipelined/src => src}/ebu/ahbinterface.sv (100%)
 rename {pipelined/src => src}/ebu/buscachefsm.sv (100%)
 rename {pipelined/src => src}/ebu/busfsm.sv (100%)
 rename {pipelined/src => src}/ebu/controllerinputstage.sv (100%)
 rename {pipelined/src => src}/ebu/ebu.sv (100%)
 rename {pipelined/src => src}/ebu/ebuarbfsm.sv (100%)
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 rename {pipelined/testbench => testbench}/testbench_imperas.sv (100%)
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diff --git a/.gitignore b/.gitignore
index 1e651e68e..b389dd1dd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,7 +15,7 @@ benchmarks/embench/wally*.json
 #vsim work files to ignore
 transcript
 vsim.wlf
-pipelined/wlft*
+wlft*
 wlft*
 /imperas-riscv-tests/FunctionRadix_32.addr
 /imperas-riscv-tests/FunctionRadix_64.addr
@@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-pipelined/regression/slack-notifier/slack-webhook-url.txt
-pipelined/regression/logs
+regression/slack-notifier/slack-webhook-url.txt
+regression/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -59,7 +59,7 @@ examples/C/sum/sum
 examples/C/fir/fir
 examples/fp/softfloat_demo/softfloat_demo
 examples/fp/fpcalc/fpcalc
-pipelined/src/fma/fma16_testgen
+src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
 linux/testvector-generation/genCheckpoint.gdb
@@ -79,29 +79,24 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-/pipelined/regression/power.saif
+regression/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv
-pipelined/srt/exptestgen
-pipelined/srt/testgen
-pipelined/srt/qslc_r4a2
-pipelined/srt/qslc_r4a2.sv
-pipelined/srt/testvectors
-pipelined/regression/wkdir
+regression/wkdir
 tests/custom/work
 tests/custom/*/*/*.list
 tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
-/pipelined/regression/sd_model.log
+regression/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
-/pipelined/regression/branch.log
+regression/branch.log
 /fpga/generator/sim/imp-funcsim.v
 /fpga/generator/sim/imp-timesim.sdf
 /fpga/generator/sim/imp-timesim.v
 /fpga/generator/sim/syn-funcsim.v
 external
-pipelined/regression/results
+regression/results
diff --git a/Install b/Install
index 7e509197d..46f4d78ec 100644
--- a/Install
+++ b/Install
@@ -328,6 +328,6 @@ source ./setup.sh        # may require some modification for your system. Always
 
   cd <to location of repo clone>
   make
-  cd pipelined/regression
+  cd regression
   ./regression-wally       #(depends on having Questa installed)
 
diff --git a/Makefile b/Makefile
index b3a054e49..24ba57e57 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ install:
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C pipelined/regression
+	make -C regression
 
 clean:
-	make clean -C pipelined/regression
+	make clean -C regression
 
diff --git a/README.md b/README.md
index 12d7fe1f6..824c7c176 100644
--- a/README.md
+++ b/README.md
@@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se
 
 Run a regression simulation with Questa to prove everything is installed.
 
-	$ cd pipelined/regression
+	$ cd regression
 	$ ./regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index 8c467d581..b8235ea94 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -21,7 +21,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	(cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
 	cd ../../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index 21c30cf6e..b5030d119 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/pipelined/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
similarity index 100%
rename from pipelined/config/buildroot/wally-config.vh
rename to config/buildroot/wally-config.vh
diff --git a/pipelined/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
similarity index 100%
rename from pipelined/config/fpga/wally-config.vh
rename to config/fpga/wally-config.vh
diff --git a/pipelined/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32e/wally-config.vh
rename to config/rv32e/wally-config.vh
diff --git a/pipelined/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32gc/wally-config.vh
rename to config/rv32gc/wally-config.vh
diff --git a/pipelined/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32i/wally-config.vh
rename to config/rv32i/wally-config.vh
diff --git a/pipelined/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32imc/wally-config.vh
rename to config/rv32imc/wally-config.vh
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64fpquad/wally-config.vh
rename to config/rv64fpquad/wally-config.vh
diff --git a/pipelined/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64gc/wally-config.vh
rename to config/rv64gc/wally-config.vh
diff --git a/pipelined/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64i/wally-config.vh
rename to config/rv64i/wally-config.vh
diff --git a/pipelined/config/shared/README b/config/shared/README
similarity index 100%
rename from pipelined/config/shared/README
rename to config/shared/README
diff --git a/pipelined/config/shared/wally-shared.vh b/config/shared/wally-shared.vh
similarity index 100%
rename from pipelined/config/shared/wally-shared.vh
rename to config/shared/wally-shared.vh
diff --git a/fpga/README.md b/fpga/README.md
index 3f9853c72..dfa27479e 100644
--- a/fpga/README.md
+++ b/fpga/README.md
@@ -16,7 +16,7 @@ a large number of debuging signals.
 
 * Programming the flash card
 You'll need to write the linux image to the flash card.  Use the convert2bin.py 
-script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
+script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt 
 file from QEMU's preload to generate the binary.  Then to copy
  sudo dd if=ram.bin of=<path to flash card>.
 
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 3ab35b34b..1d07305fb 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -27,7 +27,7 @@ SDC:
 
 PreProcessFiles:
 	rm -rf ../src/CopiedFiles_do_not_add_to_repo/
-	cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/
+	cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
 	./insert_debug_comment.sh
 
 $(dst)/%.log: %.tcl
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 45444d577..c93abed78 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -19,7 +19,7 @@ read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../s
 read_verilog  {../src/fpgaTop.v}
 read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
-set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
+set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
 
 
 add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
diff --git a/pipelined/regression/Makefile b/regression/Makefile
similarity index 100%
rename from pipelined/regression/Makefile
rename to regression/Makefile
diff --git a/pipelined/regression/buildrootBugFinder.py b/regression/buildrootBugFinder.py
similarity index 100%
rename from pipelined/regression/buildrootBugFinder.py
rename to regression/buildrootBugFinder.py
diff --git a/pipelined/regression/fpga-wave.do b/regression/fpga-wave.do
similarity index 100%
rename from pipelined/regression/fpga-wave.do
rename to regression/fpga-wave.do
diff --git a/pipelined/regression/imperas.ic b/regression/imperas.ic
similarity index 100%
rename from pipelined/regression/imperas.ic
rename to regression/imperas.ic
diff --git a/pipelined/regression/lint-wally b/regression/lint-wally
similarity index 100%
rename from pipelined/regression/lint-wally
rename to regression/lint-wally
diff --git a/pipelined/regression/linux-wave.do b/regression/linux-wave.do
similarity index 100%
rename from pipelined/regression/linux-wave.do
rename to regression/linux-wave.do
diff --git a/pipelined/regression/make-tests.sh b/regression/make-tests.sh
similarity index 88%
rename from pipelined/regression/make-tests.sh
rename to regression/make-tests.sh
index fe4555ff2..de7765086 100755
--- a/pipelined/regression/make-tests.sh
+++ b/regression/make-tests.sh
@@ -13,4 +13,4 @@ make
 # exe2memfile.pl work/*/*/*.elf
 # cd ../linux-testgen/linux-testvectors
 # ./tvLinker.sh
-# cd ../../../pipelined/regression
+# cd ../../../regression
diff --git a/pipelined/regression/makefile-memfile b/regression/makefile-memfile
similarity index 100%
rename from pipelined/regression/makefile-memfile
rename to regression/makefile-memfile
diff --git a/pipelined/regression/regression-wally b/regression/regression-wally
similarity index 100%
rename from pipelined/regression/regression-wally
rename to regression/regression-wally
diff --git a/pipelined/regression/run-imperasdv-tests.bash b/regression/run-imperasdv-tests.bash
similarity index 100%
rename from pipelined/regression/run-imperasdv-tests.bash
rename to regression/run-imperasdv-tests.bash
diff --git a/pipelined/regression/sim-buildroot b/regression/sim-buildroot
similarity index 100%
rename from pipelined/regression/sim-buildroot
rename to regression/sim-buildroot
diff --git a/pipelined/regression/sim-buildroot-batch b/regression/sim-buildroot-batch
similarity index 100%
rename from pipelined/regression/sim-buildroot-batch
rename to regression/sim-buildroot-batch
diff --git a/pipelined/regression/sim-imperas b/regression/sim-imperas
similarity index 100%
rename from pipelined/regression/sim-imperas
rename to regression/sim-imperas
diff --git a/pipelined/regression/sim-testfloat b/regression/sim-testfloat
similarity index 100%
rename from pipelined/regression/sim-testfloat
rename to regression/sim-testfloat
diff --git a/pipelined/regression/sim-testfloat-batch b/regression/sim-testfloat-batch
similarity index 100%
rename from pipelined/regression/sim-testfloat-batch
rename to regression/sim-testfloat-batch
diff --git a/pipelined/regression/sim-wally b/regression/sim-wally
similarity index 100%
rename from pipelined/regression/sim-wally
rename to regression/sim-wally
diff --git a/pipelined/regression/sim-wally-batch b/regression/sim-wally-batch
similarity index 100%
rename from pipelined/regression/sim-wally-batch
rename to regression/sim-wally-batch
diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/regression/slack-notifier/slack-notifier.py
similarity index 100%
rename from pipelined/regression/slack-notifier/slack-notifier.py
rename to regression/slack-notifier/slack-notifier.py
diff --git a/pipelined/regression/test b/regression/test
similarity index 100%
rename from pipelined/regression/test
rename to regression/test
diff --git a/pipelined/regression/testfloat.do b/regression/testfloat.do
similarity index 100%
rename from pipelined/regression/testfloat.do
rename to regression/testfloat.do
diff --git a/pipelined/regression/wally-pipelined-batch.do b/regression/wally-pipelined-batch.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-batch.do
rename to regression/wally-pipelined-batch.do
diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/regression/wally-pipelined-imperas-no-idv.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-imperas-no-idv.do
rename to regression/wally-pipelined-imperas-no-idv.do
diff --git a/pipelined/regression/wally-pipelined-imperas.do b/regression/wally-pipelined-imperas.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-imperas.do
rename to regression/wally-pipelined-imperas.do
diff --git a/pipelined/regression/wally-pipelined.do b/regression/wally-pipelined.do
similarity index 100%
rename from pipelined/regression/wally-pipelined.do
rename to regression/wally-pipelined.do
diff --git a/pipelined/regression/wave-all.do b/regression/wave-all.do
similarity index 100%
rename from pipelined/regression/wave-all.do
rename to regression/wave-all.do
diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/regression/wave-dos/ahb-muldiv.do
similarity index 100%
rename from pipelined/regression/wave-dos/ahb-muldiv.do
rename to regression/wave-dos/ahb-muldiv.do
diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/regression/wave-dos/ahb-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/ahb-waves.do
rename to regression/wave-dos/ahb-waves.do
diff --git a/pipelined/regression/wave-dos/cache-waves.do b/regression/wave-dos/cache-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/cache-waves.do
rename to regression/wave-dos/cache-waves.do
diff --git a/pipelined/regression/wave-dos/default-waves.do b/regression/wave-dos/default-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/default-waves.do
rename to regression/wave-dos/default-waves.do
diff --git a/pipelined/regression/wave-dos/generic.do b/regression/wave-dos/generic.do
similarity index 100%
rename from pipelined/regression/wave-dos/generic.do
rename to regression/wave-dos/generic.do
diff --git a/pipelined/regression/wave-dos/linux-waves.do b/regression/wave-dos/linux-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/linux-waves.do
rename to regression/wave-dos/linux-waves.do
diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/regression/wave-dos/peripheral-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/peripheral-waves.do
rename to regression/wave-dos/peripheral-waves.do
diff --git a/pipelined/regression/wave-fpu.do b/regression/wave-fpu.do
similarity index 100%
rename from pipelined/regression/wave-fpu.do
rename to regression/wave-fpu.do
diff --git a/pipelined/regression/wave.do b/regression/wave.do
similarity index 100%
rename from pipelined/regression/wave.do
rename to regression/wave.do
diff --git a/setup.imperas.sh b/setup.imperas.sh
index e3ac447bf..4e30fb07f 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
 # setup QUESTA (Imperas only command, YMMV)
 svsetup -questa
 
-pushd pipelined/regression
+pushd regression
     # With IDV
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
diff --git a/pipelined/src/cache/cache.sv b/src/cache/cache.sv
similarity index 100%
rename from pipelined/src/cache/cache.sv
rename to src/cache/cache.sv
diff --git a/pipelined/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
similarity index 100%
rename from pipelined/src/cache/cacheLRU.sv
rename to src/cache/cacheLRU.sv
diff --git a/pipelined/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
similarity index 100%
rename from pipelined/src/cache/cachefsm.sv
rename to src/cache/cachefsm.sv
diff --git a/pipelined/src/cache/cacheway.sv b/src/cache/cacheway.sv
similarity index 100%
rename from pipelined/src/cache/cacheway.sv
rename to src/cache/cacheway.sv
diff --git a/pipelined/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
similarity index 100%
rename from pipelined/src/cache/subcachelineread.sv
rename to src/cache/subcachelineread.sv
diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
similarity index 100%
rename from pipelined/src/ebu/ahbcacheinterface.sv
rename to src/ebu/ahbcacheinterface.sv
diff --git a/pipelined/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
similarity index 100%
rename from pipelined/src/ebu/ahbinterface.sv
rename to src/ebu/ahbinterface.sv
diff --git a/pipelined/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
similarity index 100%
rename from pipelined/src/ebu/buscachefsm.sv
rename to src/ebu/buscachefsm.sv
diff --git a/pipelined/src/ebu/busfsm.sv b/src/ebu/busfsm.sv
similarity index 100%
rename from pipelined/src/ebu/busfsm.sv
rename to src/ebu/busfsm.sv
diff --git a/pipelined/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv
similarity index 100%
rename from pipelined/src/ebu/controllerinputstage.sv
rename to src/ebu/controllerinputstage.sv
diff --git a/pipelined/src/ebu/ebu.sv b/src/ebu/ebu.sv
similarity index 100%
rename from pipelined/src/ebu/ebu.sv
rename to src/ebu/ebu.sv
diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/src/ebu/ebuarbfsm.sv
similarity index 100%
rename from pipelined/src/ebu/ebuarbfsm.sv
rename to src/ebu/ebuarbfsm.sv
diff --git a/pipelined/src/fpu/fclassify.sv b/src/fpu/fclassify.sv
similarity index 100%
rename from pipelined/src/fpu/fclassify.sv
rename to src/fpu/fclassify.sv
diff --git a/pipelined/src/fpu/fcmp.sv b/src/fpu/fcmp.sv
similarity index 100%
rename from pipelined/src/fpu/fcmp.sv
rename to src/fpu/fcmp.sv
diff --git a/pipelined/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
similarity index 100%
rename from pipelined/src/fpu/fctrl.sv
rename to src/fpu/fctrl.sv
diff --git a/pipelined/src/fpu/fcvt.sv b/src/fpu/fcvt.sv
similarity index 100%
rename from pipelined/src/fpu/fcvt.sv
rename to src/fpu/fcvt.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
rename to src/fpu/fdivsqrt/fdivsqrt.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
rename to src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
rename to src/fpu/fdivsqrt/fdivsqrtfgen2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
rename to src/fpu/fdivsqrt/fdivsqrtfgen4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
rename to src/fpu/fdivsqrt/fdivsqrtfsm.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
rename to src/fpu/fdivsqrt/fdivsqrtiter.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
rename to src/fpu/fdivsqrt/fdivsqrtpostproc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
rename to src/fpu/fdivsqrt/fdivsqrtpreproc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
rename to src/fpu/fdivsqrt/fdivsqrtstage2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
rename to src/fpu/fdivsqrt/fdivsqrtstage4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
rename to src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
rename to src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
diff --git a/pipelined/src/fpu/fhazard.sv b/src/fpu/fhazard.sv
similarity index 100%
rename from pipelined/src/fpu/fhazard.sv
rename to src/fpu/fhazard.sv
diff --git a/pipelined/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fma.sv
rename to src/fpu/fma/fma.sv
diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaadd.sv
rename to src/fpu/fma/fmaadd.sv
diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaalign.sv
rename to src/fpu/fma/fmaalign.sv
diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaexpadd.sv
rename to src/fpu/fma/fmaexpadd.sv
diff --git a/pipelined/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmalza.sv
rename to src/fpu/fma/fmalza.sv
diff --git a/pipelined/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmamult.sv
rename to src/fpu/fma/fmamult.sv
diff --git a/pipelined/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmasign.sv
rename to src/fpu/fma/fmasign.sv
diff --git a/pipelined/src/fpu/fpu.sv b/src/fpu/fpu.sv
similarity index 100%
rename from pipelined/src/fpu/fpu.sv
rename to src/fpu/fpu.sv
diff --git a/pipelined/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
similarity index 100%
rename from pipelined/src/fpu/fregfile.sv
rename to src/fpu/fregfile.sv
diff --git a/pipelined/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
similarity index 100%
rename from pipelined/src/fpu/fsgninj.sv
rename to src/fpu/fsgninj.sv
diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/cvtshiftcalc.sv
rename to src/fpu/postproc/cvtshiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/divshiftcalc.sv
rename to src/fpu/postproc/divshiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/flags.sv
rename to src/fpu/postproc/flags.sv
diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/fmashiftcalc.sv
rename to src/fpu/postproc/fmashiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/negateintres.sv
rename to src/fpu/postproc/negateintres.sv
diff --git a/pipelined/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/normshift.sv
rename to src/fpu/postproc/normshift.sv
diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/postprocess.sv
rename to src/fpu/postproc/postprocess.sv
diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/resultsign.sv
rename to src/fpu/postproc/resultsign.sv
diff --git a/pipelined/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/round.sv
rename to src/fpu/postproc/round.sv
diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/roundsign.sv
rename to src/fpu/postproc/roundsign.sv
diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/shiftcorrection.sv
rename to src/fpu/postproc/shiftcorrection.sv
diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/specialcase.sv
rename to src/fpu/postproc/specialcase.sv
diff --git a/pipelined/src/fpu/unpack.sv b/src/fpu/unpack.sv
similarity index 100%
rename from pipelined/src/fpu/unpack.sv
rename to src/fpu/unpack.sv
diff --git a/pipelined/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
similarity index 100%
rename from pipelined/src/fpu/unpackinput.sv
rename to src/fpu/unpackinput.sv
diff --git a/pipelined/src/generic/adder.sv b/src/generic/adder.sv
similarity index 100%
rename from pipelined/src/generic/adder.sv
rename to src/generic/adder.sv
diff --git a/pipelined/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv
similarity index 100%
rename from pipelined/src/generic/aplusbeq0.sv
rename to src/generic/aplusbeq0.sv
diff --git a/pipelined/src/generic/arrs.sv b/src/generic/arrs.sv
similarity index 100%
rename from pipelined/src/generic/arrs.sv
rename to src/generic/arrs.sv
diff --git a/pipelined/src/generic/binencoder.sv b/src/generic/binencoder.sv
similarity index 100%
rename from pipelined/src/generic/binencoder.sv
rename to src/generic/binencoder.sv
diff --git a/pipelined/src/generic/clockgater.sv b/src/generic/clockgater.sv
similarity index 100%
rename from pipelined/src/generic/clockgater.sv
rename to src/generic/clockgater.sv
diff --git a/pipelined/src/generic/counter.sv b/src/generic/counter.sv
similarity index 100%
rename from pipelined/src/generic/counter.sv
rename to src/generic/counter.sv
diff --git a/pipelined/src/generic/csa.sv b/src/generic/csa.sv
similarity index 100%
rename from pipelined/src/generic/csa.sv
rename to src/generic/csa.sv
diff --git a/pipelined/src/generic/decoder.sv b/src/generic/decoder.sv
similarity index 100%
rename from pipelined/src/generic/decoder.sv
rename to src/generic/decoder.sv
diff --git a/pipelined/src/generic/flop/flop.sv b/src/generic/flop/flop.sv
similarity index 100%
rename from pipelined/src/generic/flop/flop.sv
rename to src/generic/flop/flop.sv
diff --git a/pipelined/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopen.sv
rename to src/generic/flop/flopen.sv
diff --git a/pipelined/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenl.sv
rename to src/generic/flop/flopenl.sv
diff --git a/pipelined/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenr.sv
rename to src/generic/flop/flopenr.sv
diff --git a/pipelined/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenrc.sv
rename to src/generic/flop/flopenrc.sv
diff --git a/pipelined/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopens.sv
rename to src/generic/flop/flopens.sv
diff --git a/pipelined/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopr.sv
rename to src/generic/flop/flopr.sv
diff --git a/pipelined/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv
similarity index 100%
rename from pipelined/src/generic/flop/floprc.sv
rename to src/generic/flop/floprc.sv
diff --git a/pipelined/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv
similarity index 100%
rename from pipelined/src/generic/flop/synchronizer.sv
rename to src/generic/flop/synchronizer.sv
diff --git a/pipelined/src/generic/lzc.sv b/src/generic/lzc.sv
similarity index 100%
rename from pipelined/src/generic/lzc.sv
rename to src/generic/lzc.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
similarity index 100%
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rename to src/generic/mem/ram1p1rwbe.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv
similarity index 100%
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rename to src/generic/mem/ram1p1rwbe_64x128.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv
similarity index 100%
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rename to src/generic/mem/ram1p1rwbe_64x44.sv
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similarity index 100%
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rename to src/generic/mem/ram2p1r1wbe.sv
diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv
similarity index 100%
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rename to src/generic/mem/ram2p1r1wbe_1024x68.sv
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similarity index 100%
rename from pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
rename to src/generic/mem/ram2p1r1wbe_64x32.sv
diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r.sv
rename to src/generic/mem/rom1p1r.sv
diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r_128x32.sv
rename to src/generic/mem/rom1p1r_128x32.sv
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similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r_128x64.sv
rename to src/generic/mem/rom1p1r_128x64.sv
diff --git a/pipelined/src/generic/mux.sv b/src/generic/mux.sv
similarity index 100%
rename from pipelined/src/generic/mux.sv
rename to src/generic/mux.sv
diff --git a/pipelined/src/generic/neg.sv b/src/generic/neg.sv
similarity index 100%
rename from pipelined/src/generic/neg.sv
rename to src/generic/neg.sv
diff --git a/pipelined/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv
similarity index 100%
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rename to src/generic/onehotdecoder.sv
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similarity index 100%
rename from pipelined/src/generic/or_rows.sv
rename to src/generic/or_rows.sv
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similarity index 100%
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rename to src/generic/priorityonehot.sv
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similarity index 100%
rename from pipelined/src/generic/prioritythermometer.sv
rename to src/generic/prioritythermometer.sv
diff --git a/pipelined/src/hazard/hazard.sv b/src/hazard/hazard.sv
similarity index 100%
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rename to src/hazard/hazard.sv
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similarity index 100%
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rename to src/ieu/alu.sv
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similarity index 100%
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rename to src/ieu/comparator.sv
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similarity index 100%
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rename to src/ieu/controller.sv
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similarity index 100%
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rename to src/ieu/datapath.sv
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similarity index 100%
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rename to src/ieu/extend.sv
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similarity index 100%
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rename to src/ieu/forward.sv
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similarity index 100%
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rename to src/ieu/ieu.sv
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similarity index 100%
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rename to src/ieu/regfile.sv
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similarity index 100%
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rename to src/ieu/shifter.sv
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similarity index 100%
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rename to src/ifu/CodeAligner.py
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rename to src/ifu/bpred/RASPredictor.sv
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similarity index 100%
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rename to src/ifu/bpred/bpred.sv
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similarity index 100%
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rename to src/ifu/bpred/btb.sv
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similarity index 100%
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rename to src/ifu/bpred/foldedgshare.sv
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similarity index 100%
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rename to src/ifu/bpred/globalhistory.sv
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similarity index 100%
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rename to src/ifu/bpred/gshare.sv
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rename to src/ifu/bpred/localHistoryPredictor.sv
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similarity index 100%
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rename to src/ifu/bpred/optgshare.sv
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rename to src/ifu/bpred/speculativegshare.sv
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rename to src/ifu/bpred/twoBitPredictor.sv
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rename to src/ifu/spill.sv
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rename to src/lsu/amoalu.sv
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similarity index 100%
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rename to src/lsu/atomic.sv
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similarity index 100%
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rename to src/lsu/lsu.sv
diff --git a/pipelined/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
similarity index 100%
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rename to src/lsu/subwordread.sv
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similarity index 100%
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rename to src/lsu/subwordwrite.sv
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similarity index 100%
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similarity index 100%
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rename to src/mdu/intdivrestoring.sv
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similarity index 100%
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rename to src/mdu/intdivrestoringstep.sv
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similarity index 100%
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rename to src/mdu/mdu.sv
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similarity index 100%
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rename to src/mdu/mul.sv
diff --git a/pipelined/src/mmu/adrdec.sv b/src/mmu/adrdec.sv
similarity index 100%
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rename to src/mmu/adrdec.sv
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diff --git a/pipelined/src/mmu/hptw.sv b/src/mmu/hptw.sv
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diff --git a/pipelined/src/mmu/mmu.sv b/src/mmu/mmu.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
similarity index 100%
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rename to src/mmu/pmachecker.sv
diff --git a/pipelined/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv
similarity index 100%
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rename to src/mmu/pmpadrdec.sv
diff --git a/pipelined/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
similarity index 100%
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rename to src/mmu/pmpchecker.sv
diff --git a/pipelined/src/mmu/tlb.sv b/src/mmu/tlb.sv
similarity index 100%
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rename to src/mmu/tlb.sv
diff --git a/pipelined/src/mmu/tlbcam.sv b/src/mmu/tlbcam.sv
similarity index 100%
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rename to src/mmu/tlbcam.sv
diff --git a/pipelined/src/mmu/tlbcamline.sv b/src/mmu/tlbcamline.sv
similarity index 100%
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rename to src/mmu/tlbcamline.sv
diff --git a/pipelined/src/mmu/tlbcontrol.sv b/src/mmu/tlbcontrol.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlblru.sv b/src/mmu/tlblru.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlbmixer.sv b/src/mmu/tlbmixer.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlbram.sv b/src/mmu/tlbram.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlbramline.sv b/src/mmu/tlbramline.sv
similarity index 100%
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rename to src/mmu/tlbramline.sv
diff --git a/pipelined/src/mmu/vm64check.sv b/src/mmu/vm64check.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csr.sv b/src/privileged/csr.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrc.sv b/src/privileged/csrc.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csri.sv b/src/privileged/csri.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrm.sv b/src/privileged/csrm.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrs.sv b/src/privileged/csrs.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
similarity index 100%
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rename to src/privileged/csrsr.sv
diff --git a/pipelined/src/privileged/csru.sv b/src/privileged/csru.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/privdec.sv b/src/privileged/privdec.sv
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similarity index 100%
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diff --git a/pipelined/src/privileged/privmode.sv b/src/privileged/privmode.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/trap.sv b/src/privileged/trap.sv
similarity index 100%
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diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
similarity index 100%
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rename to src/uncore/ahbapbbridge.sv
diff --git a/pipelined/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv
similarity index 100%
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rename to src/uncore/clint_apb.sv
diff --git a/pipelined/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
similarity index 100%
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rename to src/uncore/gpio_apb.sv
diff --git a/pipelined/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
similarity index 100%
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rename to src/uncore/plic_apb.sv
diff --git a/pipelined/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
similarity index 100%
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diff --git a/pipelined/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv
similarity index 100%
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rename to src/uncore/rom_ahb.sv
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
similarity index 100%
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rename to src/uncore/uartPC16550D.sv
diff --git a/pipelined/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv
similarity index 100%
rename from pipelined/src/uncore/uart_apb.sv
rename to src/uncore/uart_apb.sv
diff --git a/pipelined/src/uncore/uncore.sv b/src/uncore/uncore.sv
similarity index 100%
rename from pipelined/src/uncore/uncore.sv
rename to src/uncore/uncore.sv
diff --git a/pipelined/src/wally/cvw.sv b/src/wally/cvw.sv
similarity index 100%
rename from pipelined/src/wally/cvw.sv
rename to src/wally/cvw.sv
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
similarity index 100%
rename from pipelined/src/wally/wallypipelinedcore.sv
rename to src/wally/wallypipelinedcore.sv
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
similarity index 100%
rename from pipelined/src/wally/wallypipelinedsoc.sv
rename to src/wally/wallypipelinedsoc.sv
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 81d37e9d2..7ef295434 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -27,7 +27,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time
 export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
-OLDCONFIGDIR ?= ${WALLY}/pipelined/config
+OLDCONFIGDIR ?= ${WALLY}/config
 export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
 CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
 CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
@@ -102,11 +102,11 @@ endif
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	cp -f ../regression/power.saif .
 endif
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	cp -f ../regression/power.saif .
 endif
 
 freqs: 
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9fd86eccc..29a0d3a35 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -19,7 +19,7 @@ set_host_options -max_cores $::env(MAXCORES)
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
 set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh
-set hdl_src "../pipelined/src"
+set hdl_src "../src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
diff --git a/pipelined/testbench/common/functionName.sv b/testbench/common/functionName.sv
similarity index 100%
rename from pipelined/testbench/common/functionName.sv
rename to testbench/common/functionName.sv
diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
similarity index 100%
rename from pipelined/testbench/common/instrNameDecTB.sv
rename to testbench/common/instrNameDecTB.sv
diff --git a/pipelined/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv
similarity index 100%
rename from pipelined/testbench/common/instrTrackerTB.sv
rename to testbench/common/instrTrackerTB.sv
diff --git a/pipelined/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
similarity index 100%
rename from pipelined/testbench/common/wallyTracer.sv
rename to testbench/common/wallyTracer.sv
diff --git a/pipelined/testbench/fp/case.sh b/testbench/fp/case.sh
similarity index 100%
rename from pipelined/testbench/fp/case.sh
rename to testbench/fp/case.sh
diff --git a/pipelined/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py
similarity index 100%
rename from pipelined/testbench/sdc/ram2sdLoad.py
rename to testbench/sdc/ram2sdLoad.py
diff --git a/pipelined/testbench/sdc/ramdisk2.hex b/testbench/sdc/ramdisk2.hex
similarity index 100%
rename from pipelined/testbench/sdc/ramdisk2.hex
rename to testbench/sdc/ramdisk2.hex
diff --git a/pipelined/testbench/sdc/run_tb.do b/testbench/sdc/run_tb.do
similarity index 100%
rename from pipelined/testbench/sdc/run_tb.do
rename to testbench/sdc/run_tb.do
diff --git a/pipelined/testbench/sdc/sdModel.sv b/testbench/sdc/sdModel.sv
similarity index 100%
rename from pipelined/testbench/sdc/sdModel.sv
rename to testbench/sdc/sdModel.sv
diff --git a/pipelined/testbench/sdc/sd_crc_16.sv b/testbench/sdc/sd_crc_16.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_crc_16.sv
rename to testbench/sdc/sd_crc_16.sv
diff --git a/pipelined/testbench/sdc/sd_crc_7.sv b/testbench/sdc/sd_crc_7.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_crc_7.sv
rename to testbench/sdc/sd_crc_7.sv
diff --git a/pipelined/testbench/sdc/sd_defines.h b/testbench/sdc/sd_defines.h
similarity index 100%
rename from pipelined/testbench/sdc/sd_defines.h
rename to testbench/sdc/sd_defines.h
diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/testbench/sdc/sd_top_tb.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_top_tb.sv
rename to testbench/sdc/sd_top_tb.sv
diff --git a/pipelined/testbench/sdc/wave.do b/testbench/sdc/wave.do
similarity index 100%
rename from pipelined/testbench/sdc/wave.do
rename to testbench/sdc/wave.do
diff --git a/pipelined/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
similarity index 99%
rename from pipelined/testbench/testbench-fp.sv
rename to testbench/testbench-fp.sv
index 62a739c40..8d6826b70 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -31,7 +31,7 @@
 
 // steps to run FMA Tests
 //    1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh
-//    2) go to riscv-wally/pipelined/testbench/fp/Tests
+//    2) go to cvw/testbench/fp/Tests
 //    3) run ./sim-fma-batch
 module testbenchfp;
   parameter TEST="none";
diff --git a/pipelined/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
similarity index 100%
rename from pipelined/testbench/testbench-linux.sv
rename to testbench/testbench-linux.sv
diff --git a/pipelined/testbench/testbench.sv b/testbench/testbench.sv
similarity index 99%
rename from pipelined/testbench/testbench.sv
rename to testbench/testbench.sv
index 853a6e001..a3fa2c093 100644
--- a/pipelined/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -238,7 +238,7 @@ logic [3:0] dummy;
       else memfilename = {pathname, tests[test], ".elf.memfile"};
       if (`FPGA) begin
         string romfilename, sdcfilename;
-        romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
         $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
         $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
diff --git a/pipelined/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
similarity index 100%
rename from pipelined/testbench/testbench_imperas.sv
rename to testbench/testbench_imperas.sv
diff --git a/pipelined/testbench/tests-fp.vh b/testbench/tests-fp.vh
similarity index 100%
rename from pipelined/testbench/tests-fp.vh
rename to testbench/tests-fp.vh
diff --git a/pipelined/testbench/tests.vh b/testbench/tests.vh
similarity index 99%
rename from pipelined/testbench/tests.vh
rename to testbench/tests.vh
index 1d094254e..f119b0a4e 100644
--- a/pipelined/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -33,13 +33,13 @@
 // *** remove MYIMPERASTEST cases when ported 
 
 string tvpaths[] = '{
-    "../../addins/imperas-riscv-tests/work/",
-    "../../tests/riscof/work/riscv-arch-test/",
-    "../../tests/riscof/work/wally-riscv-arch-test/",
-    "../../tests/imperas-riscv-tests/work/",
-    "../../benchmarks/coremark/work/",
-    "../../addins/embench-iot/",
-    "../../tests/custom/work/"
+    "../addins/imperas-riscv-tests/work/",
+    "../tests/riscof/work/riscv-arch-test/",
+    "../tests/riscof/work/wally-riscv-arch-test/",
+    "../tests/imperas-riscv-tests/work/",
+    "../benchmarks/coremark/work/",
+    "../addins/embench-iot/",
+    "../tests/custom/work/"
     };
 
   string coremark[] = '{
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
index 1fa3a9d01..414f4f2d5 100755
--- a/tests/testgen/privileged/run.sh
+++ b/tests/testgen/privileged/run.sh
@@ -11,7 +11,7 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n"
 
 if [[ "$2" != "-simonly" ]]
 then
-	cd $WALLY/pipelined/testgen/privileged
+	cd $WALLY/testgen/privileged
 	python3 "testgen-$1.py"
 	printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n"
 
@@ -48,7 +48,7 @@ fi
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
 then
 	printf "\n\n\n#####\nSimulating!\n#####\n\n"
-	cd $WALLY/pipelined/regression
+	cd $WALLY/regression
 	vsim -do wally-privileged.do -c
 fi
 

From 8078cafa2749284b4a624726e40250755a5391fc Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 14:48:23 -0800
Subject: [PATCH 05/13] Renamed regression to sim

---
 .gitignore                                     | 14 +++++++-------
 Install                                        |  2 +-
 Makefile                                       |  4 ++--
 README.md                                      |  2 +-
 benchmarks/coremark/Makefile                   |  4 ++--
 benchmarks/embench/Makefile                    |  2 +-
 setup.imperas.sh                               |  2 +-
 {regression => sim}/Makefile                   | 18 +++++++++---------
 {regression => sim}/buildrootBugFinder.py      |  0
 {regression => sim}/fpga-wave.do               |  0
 {regression => sim}/imperas.ic                 |  0
 {regression => sim}/lint-wally                 |  0
 {regression => sim}/linux-wave.do              |  0
 {regression => sim}/make-tests.sh              |  0
 {regression => sim}/makefile-memfile           |  2 +-
 {regression => sim}/regression-wally           |  0
 {regression => sim}/run-imperasdv-tests.bash   |  0
 {regression => sim}/sim-buildroot              |  0
 {regression => sim}/sim-buildroot-batch        |  0
 {regression => sim}/sim-imperas                |  0
 {regression => sim}/sim-testfloat              |  0
 {regression => sim}/sim-testfloat-batch        |  0
 {regression => sim}/sim-wally                  |  0
 {regression => sim}/sim-wally-batch            |  0
 .../slack-notifier/slack-notifier.py           |  0
 {regression => sim}/test                       |  0
 {regression => sim}/testfloat.do               |  0
 {regression => sim}/wally-pipelined-batch.do   |  0
 .../wally-pipelined-imperas-no-idv.do          |  0
 {regression => sim}/wally-pipelined-imperas.do |  0
 {regression => sim}/wally-pipelined.do         |  0
 {regression => sim}/wave-all.do                |  0
 {regression => sim}/wave-dos/ahb-muldiv.do     |  0
 {regression => sim}/wave-dos/ahb-waves.do      |  0
 {regression => sim}/wave-dos/cache-waves.do    |  0
 {regression => sim}/wave-dos/default-waves.do  |  0
 {regression => sim}/wave-dos/generic.do        |  0
 {regression => sim}/wave-dos/linux-waves.do    |  0
 .../wave-dos/peripheral-waves.do               |  0
 {regression => sim}/wave-fpu.do                |  0
 {regression => sim}/wave.do                    |  0
 synthDC/Makefile                               |  4 ++--
 tests/testgen/privileged/run.sh                |  2 +-
 43 files changed, 28 insertions(+), 28 deletions(-)
 rename {regression => sim}/Makefile (62%)
 rename {regression => sim}/buildrootBugFinder.py (100%)
 rename {regression => sim}/fpga-wave.do (100%)
 rename {regression => sim}/imperas.ic (100%)
 rename {regression => sim}/lint-wally (100%)
 rename {regression => sim}/linux-wave.do (100%)
 rename {regression => sim}/make-tests.sh (100%)
 rename {regression => sim}/makefile-memfile (99%)
 rename {regression => sim}/regression-wally (100%)
 rename {regression => sim}/run-imperasdv-tests.bash (100%)
 rename {regression => sim}/sim-buildroot (100%)
 rename {regression => sim}/sim-buildroot-batch (100%)
 rename {regression => sim}/sim-imperas (100%)
 rename {regression => sim}/sim-testfloat (100%)
 rename {regression => sim}/sim-testfloat-batch (100%)
 rename {regression => sim}/sim-wally (100%)
 rename {regression => sim}/sim-wally-batch (100%)
 rename {regression => sim}/slack-notifier/slack-notifier.py (100%)
 rename {regression => sim}/test (100%)
 rename {regression => sim}/testfloat.do (100%)
 rename {regression => sim}/wally-pipelined-batch.do (100%)
 rename {regression => sim}/wally-pipelined-imperas-no-idv.do (100%)
 rename {regression => sim}/wally-pipelined-imperas.do (100%)
 rename {regression => sim}/wally-pipelined.do (100%)
 rename {regression => sim}/wave-all.do (100%)
 rename {regression => sim}/wave-dos/ahb-muldiv.do (100%)
 rename {regression => sim}/wave-dos/ahb-waves.do (100%)
 rename {regression => sim}/wave-dos/cache-waves.do (100%)
 rename {regression => sim}/wave-dos/default-waves.do (100%)
 rename {regression => sim}/wave-dos/generic.do (100%)
 rename {regression => sim}/wave-dos/linux-waves.do (100%)
 rename {regression => sim}/wave-dos/peripheral-waves.do (100%)
 rename {regression => sim}/wave-fpu.do (100%)
 rename {regression => sim}/wave.do (100%)

diff --git a/.gitignore b/.gitignore
index b389dd1dd..5619adbff 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-regression/slack-notifier/slack-webhook-url.txt
-regression/logs
+sim/slack-notifier/slack-webhook-url.txt
+sim/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -79,24 +79,24 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-regression/power.saif
+sim/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv
-regression/wkdir
+sim/wkdir
 tests/custom/work
 tests/custom/*/*/*.list
 tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
-regression/sd_model.log
+sim/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
-regression/branch.log
+sim/branch.log
 /fpga/generator/sim/imp-funcsim.v
 /fpga/generator/sim/imp-timesim.sdf
 /fpga/generator/sim/imp-timesim.v
 /fpga/generator/sim/syn-funcsim.v
 external
-regression/results
+sim/results
diff --git a/Install b/Install
index 46f4d78ec..47a91dddd 100644
--- a/Install
+++ b/Install
@@ -328,6 +328,6 @@ source ./setup.sh        # may require some modification for your system. Always
 
   cd <to location of repo clone>
   make
-  cd regression
+  cd sim
   ./regression-wally       #(depends on having Questa installed)
 
diff --git a/Makefile b/Makefile
index 24ba57e57..1f540b56c 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ install:
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C regression
+	make -C sim
 
 clean:
-	make clean -C regression
+	make clean -C sim
 
diff --git a/README.md b/README.md
index 824c7c176..ce92151ed 100644
--- a/README.md
+++ b/README.md
@@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se
 
 Run a regression simulation with Questa to prove everything is installed.
 
-	$ cd regression
+	$ cd sim
 	$ ./regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index b8235ea94..e0aa6661d 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -21,8 +21,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
-	cd ../../benchmarks/coremark/
+	(cd ../../sim && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	cd ../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
 
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index b5030d119..0d619c90b 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../sim/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/setup.imperas.sh b/setup.imperas.sh
index 4e30fb07f..755a298b5 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
 # setup QUESTA (Imperas only command, YMMV)
 svsetup -questa
 
-pushd regression
+pushd sim
     # With IDV
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
diff --git a/regression/Makefile b/sim/Makefile
similarity index 62%
rename from regression/Makefile
rename to sim/Makefile
index adc7bc718..6a917bcda 100644
--- a/regression/Makefile
+++ b/sim/Makefile
@@ -2,27 +2,27 @@ all: riscoftests memfiles
 	# *** Build old tests/imperas-riscv-tests for now;
 	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
 	# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
-	#make -C ../../tests/imperas-riscv-tests --jobs
-	#make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs
+	#make -C ../tests/imperas-riscv-tests --jobs
+	#make -C ../tests/imperas-riscv-tests XLEN=64 --jobs
 	# Only compile Imperas tests if they are installed locally.  
 	# They are usually a symlink to $RISCV/imperas-riscv-tests and only 
 	# get compiled there manually during installation
-	#make -C ../../addins/imperas-riscv-tests
-	#make -C ../../addins/imperas-riscv-tests XLEN=64
-	#cd ../../addins/imperas-riscv-tests; elf2hex.sh
-	#cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
+	#make -C ../addins/imperas-riscv-tests
+	#make -C ../addins/imperas-riscv-tests XLEN=64
+	#cd ../addins/imperas-riscv-tests; elf2hex.sh
+	#cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
 	# Link Linux test vectors 
-	#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
+	#cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
 
 allclean: clean all
 
 clean:
-	make clean -C ../../tests/riscof
+	make clean -C ../tests/riscof
 #   make clean -C ../../tests/wally-riscv-arch-test
 #	make allclean -C ../../tests/imperas-riscv-tests
 
 riscoftests: 
 # 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
-	make -C ../../tests/riscof/ 
+	make -C ../tests/riscof/ 
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs
diff --git a/regression/buildrootBugFinder.py b/sim/buildrootBugFinder.py
similarity index 100%
rename from regression/buildrootBugFinder.py
rename to sim/buildrootBugFinder.py
diff --git a/regression/fpga-wave.do b/sim/fpga-wave.do
similarity index 100%
rename from regression/fpga-wave.do
rename to sim/fpga-wave.do
diff --git a/regression/imperas.ic b/sim/imperas.ic
similarity index 100%
rename from regression/imperas.ic
rename to sim/imperas.ic
diff --git a/regression/lint-wally b/sim/lint-wally
similarity index 100%
rename from regression/lint-wally
rename to sim/lint-wally
diff --git a/regression/linux-wave.do b/sim/linux-wave.do
similarity index 100%
rename from regression/linux-wave.do
rename to sim/linux-wave.do
diff --git a/regression/make-tests.sh b/sim/make-tests.sh
similarity index 100%
rename from regression/make-tests.sh
rename to sim/make-tests.sh
diff --git a/regression/makefile-memfile b/sim/makefile-memfile
similarity index 99%
rename from regression/makefile-memfile
rename to sim/makefile-memfile
index 646da5ac3..6c2da42fa 100644
--- a/regression/makefile-memfile
+++ b/sim/makefile-memfile
@@ -1,4 +1,4 @@
-ROOT	:= ../..
+ROOT	:= ..
 SUFFIX	:= work
 ARCHDIR	:= $(ROOT)/tests/riscof
 WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
diff --git a/regression/regression-wally b/sim/regression-wally
similarity index 100%
rename from regression/regression-wally
rename to sim/regression-wally
diff --git a/regression/run-imperasdv-tests.bash b/sim/run-imperasdv-tests.bash
similarity index 100%
rename from regression/run-imperasdv-tests.bash
rename to sim/run-imperasdv-tests.bash
diff --git a/regression/sim-buildroot b/sim/sim-buildroot
similarity index 100%
rename from regression/sim-buildroot
rename to sim/sim-buildroot
diff --git a/regression/sim-buildroot-batch b/sim/sim-buildroot-batch
similarity index 100%
rename from regression/sim-buildroot-batch
rename to sim/sim-buildroot-batch
diff --git a/regression/sim-imperas b/sim/sim-imperas
similarity index 100%
rename from regression/sim-imperas
rename to sim/sim-imperas
diff --git a/regression/sim-testfloat b/sim/sim-testfloat
similarity index 100%
rename from regression/sim-testfloat
rename to sim/sim-testfloat
diff --git a/regression/sim-testfloat-batch b/sim/sim-testfloat-batch
similarity index 100%
rename from regression/sim-testfloat-batch
rename to sim/sim-testfloat-batch
diff --git a/regression/sim-wally b/sim/sim-wally
similarity index 100%
rename from regression/sim-wally
rename to sim/sim-wally
diff --git a/regression/sim-wally-batch b/sim/sim-wally-batch
similarity index 100%
rename from regression/sim-wally-batch
rename to sim/sim-wally-batch
diff --git a/regression/slack-notifier/slack-notifier.py b/sim/slack-notifier/slack-notifier.py
similarity index 100%
rename from regression/slack-notifier/slack-notifier.py
rename to sim/slack-notifier/slack-notifier.py
diff --git a/regression/test b/sim/test
similarity index 100%
rename from regression/test
rename to sim/test
diff --git a/regression/testfloat.do b/sim/testfloat.do
similarity index 100%
rename from regression/testfloat.do
rename to sim/testfloat.do
diff --git a/regression/wally-pipelined-batch.do b/sim/wally-pipelined-batch.do
similarity index 100%
rename from regression/wally-pipelined-batch.do
rename to sim/wally-pipelined-batch.do
diff --git a/regression/wally-pipelined-imperas-no-idv.do b/sim/wally-pipelined-imperas-no-idv.do
similarity index 100%
rename from regression/wally-pipelined-imperas-no-idv.do
rename to sim/wally-pipelined-imperas-no-idv.do
diff --git a/regression/wally-pipelined-imperas.do b/sim/wally-pipelined-imperas.do
similarity index 100%
rename from regression/wally-pipelined-imperas.do
rename to sim/wally-pipelined-imperas.do
diff --git a/regression/wally-pipelined.do b/sim/wally-pipelined.do
similarity index 100%
rename from regression/wally-pipelined.do
rename to sim/wally-pipelined.do
diff --git a/regression/wave-all.do b/sim/wave-all.do
similarity index 100%
rename from regression/wave-all.do
rename to sim/wave-all.do
diff --git a/regression/wave-dos/ahb-muldiv.do b/sim/wave-dos/ahb-muldiv.do
similarity index 100%
rename from regression/wave-dos/ahb-muldiv.do
rename to sim/wave-dos/ahb-muldiv.do
diff --git a/regression/wave-dos/ahb-waves.do b/sim/wave-dos/ahb-waves.do
similarity index 100%
rename from regression/wave-dos/ahb-waves.do
rename to sim/wave-dos/ahb-waves.do
diff --git a/regression/wave-dos/cache-waves.do b/sim/wave-dos/cache-waves.do
similarity index 100%
rename from regression/wave-dos/cache-waves.do
rename to sim/wave-dos/cache-waves.do
diff --git a/regression/wave-dos/default-waves.do b/sim/wave-dos/default-waves.do
similarity index 100%
rename from regression/wave-dos/default-waves.do
rename to sim/wave-dos/default-waves.do
diff --git a/regression/wave-dos/generic.do b/sim/wave-dos/generic.do
similarity index 100%
rename from regression/wave-dos/generic.do
rename to sim/wave-dos/generic.do
diff --git a/regression/wave-dos/linux-waves.do b/sim/wave-dos/linux-waves.do
similarity index 100%
rename from regression/wave-dos/linux-waves.do
rename to sim/wave-dos/linux-waves.do
diff --git a/regression/wave-dos/peripheral-waves.do b/sim/wave-dos/peripheral-waves.do
similarity index 100%
rename from regression/wave-dos/peripheral-waves.do
rename to sim/wave-dos/peripheral-waves.do
diff --git a/regression/wave-fpu.do b/sim/wave-fpu.do
similarity index 100%
rename from regression/wave-fpu.do
rename to sim/wave-fpu.do
diff --git a/regression/wave.do b/sim/wave.do
similarity index 100%
rename from regression/wave.do
rename to sim/wave.do
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 7ef295434..f13b38ab6 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -102,11 +102,11 @@ endif
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../regression/power.saif .
+	cp -f ../sim/power.saif .
 endif
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../regression/power.saif .
+	cp -f ../sim/power.saif .
 endif
 
 freqs: 
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
index 414f4f2d5..d1afb4e89 100755
--- a/tests/testgen/privileged/run.sh
+++ b/tests/testgen/privileged/run.sh
@@ -48,7 +48,7 @@ fi
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
 then
 	printf "\n\n\n#####\nSimulating!\n#####\n\n"
-	cd $WALLY/regression
+	cd $WALLY/sim
 	vsim -do wally-privileged.do -c
 fi
 

From a9226e6f73b9ccda7554e4840041e7d6d280c42c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 19:40:41 -0800
Subject: [PATCH 06/13] Removed lab1matrix solutions

---
 examples/C/lab1matrix/Makefile  |  33 ------------
 examples/C/lab1matrix/matMult   | Bin 43352 -> 0 bytes
 examples/C/lab1matrix/matMult.c |  87 --------------------------------
 3 files changed, 120 deletions(-)
 delete mode 100644 examples/C/lab1matrix/Makefile
 delete mode 100755 examples/C/lab1matrix/matMult
 delete mode 100644 examples/C/lab1matrix/matMult.c

diff --git a/examples/C/lab1matrix/Makefile b/examples/C/lab1matrix/Makefile
deleted file mode 100644
index 18c011f4f..000000000
--- a/examples/C/lab1matrix/Makefile
+++ /dev/null
@@ -1,33 +0,0 @@
-TARGET = matMult
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-	spike $(TARGET)
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../common/test.ld -I../common \
-	  $(TARGET).c ../common/crt.S ../common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult
deleted file mode 100755
index e3d3b25dd44f3d863bf10fb093a7f51972edf99a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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zVM)~Ke1*V(E_A;j5BDAPEeJ<qc^wX}k@5ULg?ob$p^BO5Tn!2`3HuN=MqKU)n81Pf
zBNEJbeepcY)>Yo$nO0|A;d&l`sQyjf5F<6kdof!9%;czRENa9*+F*HKa_j<)m}Kx=
zusGtOYcl=_X1Tn78FnGH;=eI4p{_dXp{a_?0gy}{Kd*zEF47d)x^O<Ze@0vdK=B*H
zavo&<DNJa}i7|D0WiCcVMZx@U&_*%hilr?<TP%*q7tz9w3wNfYu2|Yyw8r9yq3jyX
zc3odx@@Fh<0~%s+MEf!={J3t@h4Y!}KpMCe#o725Ez|9n#x%xM#m?{G-)Rnl|4I`i
z;)><}7qk&>WCRU?GjG?3r#Uc8JM(jS0Qj@<C*GkM9%sVu;D6>j_@8al46!>)7RTl9
zKn4}bjZxR14ZoQNP8;(v;vE37IBM(h6HW1Q%=lyDpLluhX%78)j5c7nc6oG3VT@n;
sR&#|gJ?H}$od{yOQ25RFs6rIQC>K*zJMy#fAKk6_KhcHr8O#6w07E3%>;M1&

diff --git a/examples/C/lab1matrix/matMult.c b/examples/C/lab1matrix/matMult.c
deleted file mode 100644
index b794819f9..000000000
--- a/examples/C/lab1matrix/matMult.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// matMult.c
-// mmasserfrye@hmc.edu 30 January 2022
-
-#include <stdio.h>  // supports printf
-#include <math.h>   // supports fabs
-#include "util.h"   // supports verify
-
-// puts the indicated row of length n from matrix mat into array arr
-void getRow(int n, int row, double *mat, double *arr){
-    int ind;
-    for (int i=0; i<n; i++){
-        ind = i+row*n;
-        arr[i] = mat[ind];
-    }
-}
-
-// computes the dot product of arrays a and b of length n
-double dotproduct(int n, double a[], double b[]) {
-
-    volatile int i;
-    double sum;
-    sum = 0;
-
-    for (i=0; i<n; i++) {
-        if (i==0) sum=0;
-        sum += a[i]*b[i];
-    }
-    return sum;
-}
-
-// multiplies matrices A (m1 x n1m2) and B (n1m2 x n2) and puts the result in Y
-void mult(int m1, int n1m2, int n2, double *A, double *B, double *Y) {
-
-    // transpose B into Bt so we can dot product matching rows
-    double Bt[n2*n1m2];
-    int ind;
-    int indt;
-    for (int i=0; i<n1m2; i++){
-        for (int j=0; j<n2; j++){
-            ind = i*n2+j;
-            indt = j*n1m2+i;
-            Bt[indt] = B[ind];
-        }
-    }
-
-    int indY;
-    double Arow[n1m2];
-    double Bcol[n1m2];
-
-    for (int i=0; i<m1; i++){
-        for (int j=0; j<n2; j++){
-            indY = i*n2+j;
-            getRow(n1m2, i, A, Arow);
-            getRow(n1m2, j, Bt, Bcol);
-            Y[indY] = dotproduct(n1m2, Arow, Bcol);
-        }
-    }
-}
-
-int main(void) {
-
-    // change these bits to test stuff
-    int m = 20;
-    int n = 1;
-    double X[20]; // change to m*n
-    double Y[400]; // change to m^2
-
-    // fill in some numbers so the test feels legit
-    for (int i=0; i<n; i++){
-        X[i] = i;
-    }
- 
-    setStats(1);
-    mult(m, n, m, X, X, Y);
-    setStats(0);
-
-    /*
-    // use this code from Harris's fir.c to print matrix one element at a time
-    // library linked doesn't support printing doubles, so convert to integers to print
-    for (int i=0; i<m*m; i++)  {
-        int tmp = Y[i];
-        printf("Y[%d] = %d\n", i, tmp);
-    }
-    */
-    return 0;
-    
-}
\ No newline at end of file

From 398992db3bb303849c3b273e21dda082122eb571 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 3 Feb 2023 08:36:03 -0800
Subject: [PATCH 07/13] Updated division radix test script with paths, but
 script is out of date for files it manipulates

---
 bin/radixcopiesmultiregression.sh | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh
index 1953b1da4..f701dada2 100755
--- a/bin/radixcopiesmultiregression.sh
+++ b/bin/radixcopiesmultiregression.sh
@@ -10,39 +10,39 @@ currCopies="define DIVCOPIES 32'h1"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h2"
 currCopies="define DIVCOPIES 32'h2"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h2"
 currCopies="define DIVCOPIES 32'h4"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h1"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h2"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h4"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
\ No newline at end of file
+./sim/regression-wally
\ No newline at end of file

From ed02d5a0774023ee631f22710f09e3d833c21ce9 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 3 Feb 2023 08:36:51 -0800
Subject: [PATCH 08/13] Removed redundant line from synthesis makefile

---
 synthDC/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index f13b38ab6..c715a88b4 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -24,7 +24,6 @@ export DRIVE ?= FLOP
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
 export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/config

From d9e1323e57d2c467b5305b511c1954604be7402a Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Sat, 4 Feb 2023 09:50:36 +0000
Subject: [PATCH 09/13] added use sram parameter, cleaned up config writing,
 added single synth functionality to wallySynth

---
 synthDC/Makefile          | 79 +++++++++++++++++----------------------
 synthDC/scripts/synth.tcl |  3 +-
 synthDC/wallySynth.py     | 17 ++++++---
 3 files changed, 47 insertions(+), 52 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 81d37e9d2..fdfc9e488 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -12,7 +12,7 @@ export MOD ?= orig
 # title to add a note in the synth's directory name
 TITLE = 
 # tsmc28, sky130, and sky90 presently supported
-export TECH ?= sky90
+export TECH ?= tsmc28
 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient
 # Avoid when doing sweeps of many optimization points in parallel
 export MAXCORES ?= 1
@@ -20,6 +20,7 @@ export MAXCORES ?= 1
 # The output netlist is hard to interpret, but significantly better PPA
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
+export USESRAM ?= 0
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
@@ -29,13 +30,7 @@ export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/pipelined/config
 export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
-CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
-CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
 
-print:
-	@echo $(FREQS)
-	@echo $(CONFIG)
-	@echo $(CONFIGFILESTRIM)
 
 
 default:
@@ -46,8 +41,6 @@ default:
 
 DIRS32 = rv32e rv32gc rv32imc rv32i
 DIRS64 = rv64i rv64gc
-DIRS32 = rv32e rv32gc rv32ic rv32i
-DIRS64 = rv64i rv64gc
 DIRS = $(DIRS32) $(DIRS64)
 
 # k = 3 6 
@@ -60,57 +53,55 @@ DIRS = $(DIRS32) $(DIRS64)
 configs: $(CONFIG)
 $(CONFIG):
 	@echo $(CONFIG)
-	cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig
-	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
+	cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
+	cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
 
-ifneq ($(filter $ $(CONFIG), $(DIRS32)),)
-	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-else ifneq ($(filter $ $(CONFIG), $(DIRS64)),)
-	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
+ifeq ($(USESRAM), 1)
+	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh
+
+else
+	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
+
+ifneq ($(filter $(CONFIG), $(DIRS32)),)
+	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+else ifneq ($(filter $(CONFIG), $(DIRS64)),)
+	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
 else 
 	$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
 	@echo "Config not in list, RAM_RANGE will be unmodified"
 endif
+endif
 	
+ifeq ($(MOD), FPUoff)
 	# turn off FPU 
-	cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff
-	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
-	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
-
+	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), PMP16)
 	# PMP 16 
-	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16
-	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh
-	
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), PMP0)
 	# PMP 0
-	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
-	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
-	
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), noMulDiv)
 	# no muldiv
-	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
-	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
-
+	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), noPriv)
 	# no priv
-	cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
-	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
-
-ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh
 endif
 
 ifeq ($(SAIFPOWER), 1)
 	cp -f ../pipelined/regression/power.saif .
 endif
 
-freqs: 
-	@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
 
 mkdirecs:
 	@echo "DC Synthesis"
@@ -129,7 +120,7 @@ rundc:
 	
 	
 clean:
-	rm -rf $(OUTPUTDIR)/hdl
+	rm -rf $(OUTPUTDIR)/hdl/*.sv
 	rm -rf $(OUTPUTDIR)/WORK
 	rm -rf $(OUTPUTDIR)/alib-52
 	rm -f default.svf
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9fd86eccc..d7e792569 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -18,7 +18,7 @@ set_host_options -max_cores $::env(MAXCORES)
 
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
-set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh
+set cfg $::env(CONFIGDIR)/wally-config.vh
 set hdl_src "../pipelined/src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
@@ -26,7 +26,6 @@ set drive $::env(DRIVE)
 
 eval file copy -force $cfg {$outputDir/hdl/}
 eval file copy -force $cfg {$outputDir/}
-eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 9ac3a995d..5015b8ca7 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -5,9 +5,9 @@ import subprocess
 from multiprocessing import Pool
 import argparse
 
-def runSynth(config, mod, tech, freq, maxopt):
+def runSynth(config, mod, tech, freq, maxopt, usesram):
     global pool
-    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt)
+    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
     pool.map(mask, [command])
 
 def mask(command):
@@ -32,6 +32,7 @@ if __name__ == '__main__':
     parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy")
     parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
     parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
+    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM (not flops)")
 
     args = parser.parse_args()
 
@@ -39,17 +40,21 @@ if __name__ == '__main__':
     defaultfreq = 3000 if tech == 'sky90' else 10000
     freq = args.targetfreq if args.targetfreq else defaultfreq
     maxopt = int(args.maxopt)
-    mod = 'orig' # until memory integrated
+    usesram = int(args.usesram)
+    mod = 'orig'
 
     if args.freqsweep:
         sc = args.freqsweep
         config = args.version if args.version else 'rv32e'
         for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
-            runSynth(config, mod, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt, usesram)
     if args.configsweep:
         for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
-            runSynth(config, mod, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt, usesram)
     if args.featuresweep:
         config = args.version if args.version else 'rv64gc'
         for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', 
-            runSynth(config, mod, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt, usesram)
+    else:
+        config = args.version if args.version else 'rv64gc'
+        runSynth(config, mod, tech, freq, maxopt, usesram)
\ No newline at end of file

From 7b0da71297c13317084f5f2b7b07fc547202d959 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Sat, 4 Feb 2023 10:24:01 +0000
Subject: [PATCH 10/13] finishing the job of the last commit

---
 synthDC/Makefile          | 8 ++++----
 synthDC/scripts/synth.tcl | 5 ++---
 synthDC/wallySynth.py     | 4 ++--
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index fdfc9e488..fd9667942 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -29,7 +29,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/pipelined/config
-export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
+export CONFIGDIR ?= $(OUTPUTDIR)/config
 
 
 
@@ -106,8 +106,8 @@ endif
 mkdirecs:
 	@echo "DC Synthesis"
 	@mkdir -p $(OUTPUTDIR)
-	@mkdir -p $(OUTPUTDIR)/hdl/config
-	@mkdir -p $(OUTPUTDIR)/hdl/config
+	@mkdir -p $(OUTPUTDIR)/hdl
+	@mkdir -p $(OUTPUTDIR)/config
 	@mkdir -p $(OUTPUTDIR)/reports
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
@@ -120,7 +120,7 @@ rundc:
 	
 	
 clean:
-	rm -rf $(OUTPUTDIR)/hdl/*.sv
+	rm -rf $(OUTPUTDIR)/hdl
 	rm -rf $(OUTPUTDIR)/WORK
 	rm -rf $(OUTPUTDIR)/alib-52
 	rm -f default.svf
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index d7e792569..ba6e4bb96 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -18,14 +18,13 @@ set_host_options -max_cores $::env(MAXCORES)
 
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
-set cfg $::env(CONFIGDIR)/wally-config.vh
+set cfg $::env(CONFIGDIR)
 set hdl_src "../pipelined/src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
 
-eval file copy -force $cfg {$outputDir/hdl/}
-eval file copy -force $cfg {$outputDir/}
+eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 5015b8ca7..3c96c38ee 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -1,5 +1,5 @@
 #!/usr/bin/python3
-# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22
+# Madeleine Masser-Frye mmasserfrye@hmc.edu 1/2023
 
 import subprocess
 from multiprocessing import Pool
@@ -32,7 +32,7 @@ if __name__ == '__main__':
     parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy")
     parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
     parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
-    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM (not flops)")
+    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules")
 
     args = parser.parse_args()
 

From e0915acad9c141c6ad6e106094c2841c1915097d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 03:42:20 -0800
Subject: [PATCH 11/13] Improved illegal NaN-box detection and formatted
 fsgninj

---
 src/fpu/fsgninj.sv     | 18 +++++++++---------
 src/fpu/unpack.sv      | 11 +++++------
 src/fpu/unpackinput.sv | 25 ++++++++++++++-----------
 3 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
index d5568cabe..0db7dc2f3 100755
--- a/src/fpu/fsgninj.sv
+++ b/src/fpu/fsgninj.sv
@@ -29,11 +29,11 @@
 `include "wally-config.vh"
 
 module fsgninj (  
-	input  logic        		Xs, Ys,	// X and Y sign bits
-	input  logic [`FLEN-1:0] 	X,		// X
-	input  logic [`FMTBITS-1:0]	Fmt,	// format
-	input  logic [1:0]  		OpCtrl,	// operation control
-	output logic [`FLEN-1:0] 	SgnRes	// result
+	input  logic        		    Xs, Ys,	// X and Y sign bits
+	input  logic [`FLEN-1:0] 	  X,		  // X
+	input  logic [`FMTBITS-1:0]	Fmt,	  // format
+	input  logic [1:0]  		    OpCtrl,	// operation control
+	output logic [`FLEN-1:0] 	  SgnRes	// result
 );
 
 	logic ResSgn;	// result sign
@@ -54,13 +54,13 @@ module fsgninj (
 		assign SgnRes = {ResSgn, X[`FLEN-2:0]};
   else if (`FPSIZES == 2)
 		assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]};
-  else if (`FPSIZES == 3) begin
+  else if (`FPSIZES ==  3) begin
 		logic [2:0] SgnBits;
     always_comb
       case (Fmt)
-        `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
-        `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
-        `FMT2: SgnBits = {2'b11, ResSgn};
+        `FMT:    SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
+  	    `FMT1:   SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
+        `FMT2:   SgnBits = {2'b11, ResSgn};
         default: SgnBits = {3{1'bx}};
       endcase
 		assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]};
diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv
index 13addc2e3..356d7e897 100644
--- a/src/fpu/unpack.sv
+++ b/src/fpu/unpack.sv
@@ -48,15 +48,14 @@ module unpack (
   
   unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
                           .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
-                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero));
+                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm));
 
   unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
                           .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
-                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero));
+                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm());
 
   unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
                           .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
-                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
-  // is the input subnormal
-  assign XSubnorm = ~XExpNonZero & ~XFracZero;
-endmodule
\ No newline at end of file
+                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm());
+ 
+ endmodule
\ No newline at end of file
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index 34663bd8c..b85077d20 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -31,16 +31,17 @@ module unpackinput (
   input  logic [`FLEN-1:0]        In,         // inputs from register file
   input  logic                    En,         // enable the input
   input  logic [`FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
-  output logic                    Sgn,        // sign bits of XYZ
-  output logic [`NE-1:0]          Exp,        // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]            Man,        // mantissas of XYZ (converted to largest supported precision)
-  output logic                    NaN,        // is XYZ a NaN
-  output logic                    SNaN,       // is XYZ a signaling NaN
-  output logic                    Zero,       // is XYZ zero
-  output logic                    Inf,        // is XYZ infinity
+  output logic                    Sgn,        // sign bits of the number 
+  output logic [`NE-1:0]          Exp,        // exponent of the number  (converted to largest supported precision)
+  output logic [`NF:0]            Man,        // mantissa of the number  (converted to largest supported precision)
+  output logic                    NaN,        // is the number a NaN
+  output logic                    SNaN,       // is the number a signaling NaN
+  output logic                    Zero,       // is the number zero
+  output logic                    Inf,        // is the number infinity
   output logic                    ExpNonZero, // is the exponent not zero
   output logic                    FracZero,   // is the fraction zero
-  output logic                    ExpMax      // does In have the maximum exponent (NaN or Inf)
+  output logic                    ExpMax,      // does In have the maximum exponent (NaN or Inf)
+  output logic                    Subnorm     // is the number subnormal
 );
 
   logic [`NF-1:0] Frac;       // Fraction of XYZ
@@ -261,10 +262,12 @@ module unpackinput (
   end
 
   // Output logic
-  assign FracZero = ~|Frac; // is the fraction zero?
+  assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero?
   assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
   assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
   assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
-  assign Inf = ExpMax & FracZero &En; // is the input infinity?
-  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
+  assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity?
+  assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero?
+  assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
+
 endmodule
\ No newline at end of file

From 6b3d0567133f5f535048dbff7c4e2162d27561f3 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 04:19:09 -0800
Subject: [PATCH 12/13] ../synthDC/Makefile

---
 synthDC/Makefile | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 4d39e7c87..613ca49af 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -57,27 +57,17 @@ $(CONFIG):
 
 ifeq ($(USESRAM), 1)
 	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh
-
 else
 	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
 
-  @echo "match32"
-  @echo $(filter $(CONFIG), $(DIRS32))
-  @echo "match64"
-  @echo $(filter $(CONFIG), $(DIRS64))
-
   ifneq ($(filter $(CONFIG), $(DIRS32)),)
     sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
     sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
   else ifneq ($(filter $(CONFIG), $(DIRS64)),)
     sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
     sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
   else 
     $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
     @echo "Config not in list, RAM_RANGE will be unmodified"

From 3f22b626010be2258c3af6e2c047cb401c96ebd7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 04:29:27 -0800
Subject: [PATCH 13/13] Added license headers

---
 Makefile                                    |   4 +
 benchmarks/coremark/Makefile                |   1 +
 benchmarks/coremark/coremark-postprocess.py |  12 +-
 benchmarks/graphGen.py                      |   3 +
 bin/radixcopiesmultiregression.sh           |   2 +
 setup.sh                                    |   1 +
 wallypipelinedcore.sv                       | 360 --------------------
 wallypipelinedsoc.sv                        |  92 -----
 8 files changed, 12 insertions(+), 463 deletions(-)
 delete mode 100644 wallypipelinedcore.sv
 delete mode 100644 wallypipelinedsoc.sv

diff --git a/Makefile b/Makefile
index 1f540b56c..518bcd2dd 100644
--- a/Makefile
+++ b/Makefile
@@ -1,3 +1,7 @@
+# David_Harris@hmc.edu 2023
+# Top-level Makefile for CORE-V-Wally
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 all:
 	make install
 	make regression
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index e0aa6661d..bb0f20f5a 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -1,5 +1,6 @@
 # Wally Coremark Makefile
 # Daniel Torres & David Harris 28 July 2022
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 PORT_DIR = $(CURDIR)/riscv64-baremetal
 cmbase=../../addins/coremark
diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py
index d069e8744..f77f2ef8b 100644
--- a/benchmarks/coremark/coremark-postprocess.py
+++ b/benchmarks/coremark/coremark-postprocess.py
@@ -9,17 +9,7 @@
 #
 # Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 #
-# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-# is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 ##################################################
 
 logFile = "../../benchmarks/coremark/work/coremark.sim.log"
diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py
index de8b70ce9..dd7b3a204 100755
--- a/benchmarks/graphGen.py
+++ b/benchmarks/graphGen.py
@@ -1,4 +1,7 @@
 #!/usr/bin/env python
+# Daniel Torres 2022
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 import subprocess
 import sys
 import json
diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh
index f701dada2..5d4f3f653 100755
--- a/bin/radixcopiesmultiregression.sh
+++ b/bin/radixcopiesmultiregression.sh
@@ -1,4 +1,6 @@
 #!/bin/bash
+# Alessandro Maiuolo 2022
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 configFile=config/shared/wally-shared.vh
 
diff --git a/setup.sh b/setup.sh
index d54ae7bd4..af4bac3b5 100755
--- a/setup.sh
+++ b/setup.sh
@@ -3,6 +3,7 @@
 # setup.sh
 # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
 # Set up tools for rvw
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 echo "Executing Wally setup.sh"
 
diff --git a/wallypipelinedcore.sv b/wallypipelinedcore.sv
deleted file mode 100644
index 7013d0309..000000000
--- a/wallypipelinedcore.sv
+++ /dev/null
@@ -1,360 +0,0 @@
-///////////////////////////////////////////
-// wallypipelinedcore.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Pipelined RISC-V Processor
-// 
-// Documentation: RISC-V System on Chip Design (Figure 4.1)
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-import cvw::*;  // global CORE-V-Wally parameters
-
-module wallypipelinedcore (
-   input  logic                  clk, reset,
-   // Privileged
-   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
-   input  logic [63:0]           MTIME_CLINT, 
-   // Bus Interface
-   input  logic [AHBW-1:0]       HRDATA,
-   input  logic                  HREADY, HRESP,
-   output logic                  HCLK, HRESETn,
-   output logic [PA_BITS-1:0]    HADDR,
-   output logic [AHBW-1:0]       HWDATA,
-   output logic [XLEN/8-1:0]     HWSTRB,
-   output logic                  HWRITE,
-   output logic [2:0]            HSIZE,
-   output logic [2:0]            HBURST,
-   output logic [3:0]            HPROT,
-   output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
-);
-
-  logic                          StallF, StallD, StallE, StallM, StallW;
-  logic                          FlushD, FlushE, FlushM, FlushW;
-  logic                          RetM;
-  logic TrapM;
-
-  //  signals that must connect through DP
-  logic                          IntDivE, W64E;
-  logic                          CSRReadM, CSRWriteM, PrivilegedM;
-  logic [1:0]                    AtomicM;
-  logic [XLEN-1:0]               ForwardedSrcAE, ForwardedSrcBE;
-  logic [XLEN-1:0] 			  SrcAM;
-  logic [2:0]                    Funct3E;
-  logic [31:0]                   InstrD;
-  logic [31:0] 					 InstrM;
-  logic [XLEN-1:0]               PCFSpill, PCE, PCLinkE;
-  logic [XLEN-1:0] 			  PCM;
-  logic [XLEN-1:0]               CSRReadValW, MDUResultW;
-  logic [XLEN-1:0]               UnalignedPCNextF, PCNext2F;
-  logic [1:0] 					 MemRWM;
-  logic 						 InstrValidM;
-  logic                          InstrMisalignedFaultM;
-  logic                          IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
-  logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
-  logic                          LoadMisalignedFaultM, LoadAccessFaultM;
-  logic                          StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
-  logic                          InvalidateICacheM, FlushDCacheM;
-  logic                          PCSrcE;
-  logic                          CSRWriteFenceM;
-  logic                          DivBusyE;
-  logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
-  logic                          SquashSCW;
-
-  // floating point unit signals
-  logic [2:0]                    FRM_REGW;
-  logic [4:0]                    RdE, RdM, RdW;
-  logic                          FPUStallD;
-  logic                          FWriteIntE;
-  logic [FLEN-1:0]               FWriteDataM;
-  logic [XLEN-1:0]               FIntResM;  
-  logic [XLEN-1:0]              FCvtIntResW; 
-  logic                          FCvtIntW; 
-  logic                          FDivBusyE;
-  logic                          IllegalFPUInstrM;
-  logic                          FRegWriteM;
-  logic                          FCvtIntStallD;
-  logic                          FpLoadStoreM;
-  logic [4:0]                    SetFflagsM;
-  logic [XLEN-1:0]               FIntDivResultW;
-
-  // memory management unit signals
-  logic                          ITLBWriteF;
-  logic                          ITLBMissF;
-  logic [XLEN-1:0]               SATP_REGW;
-  logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
-  logic  [1:0]                   STATUS_MPP, STATUS_FS;
-  logic [1:0]                    PrivilegeModeW;
-  logic [XLEN-1:0]               PTE;
-  logic [1:0]                    PageType;
-  logic                          sfencevmaM, WFIStallM;
-  logic                          SelHPTW;
-
-  // PMA checker signals
-  var logic [XLEN-1:0]           PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
-  var logic [7:0]                PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
-
-  // IMem stalls
-  logic                          IFUStallF;
-  logic                          LSUStallM;
-
-  // cpu lsu interface
-  logic [2:0]                    Funct3M;
-  logic [XLEN-1:0]               IEUAdrE;
-  logic [XLEN-1:0]  WriteDataM;
-  logic [XLEN-1:0]  IEUAdrM;  
-  logic [LLEN-1:0]               ReadDataW;  
-  logic                          CommittedM;
-
-  // AHB ifu interface
-  logic [PA_BITS-1:0]            IFUHADDR;
-  logic [2:0]                    IFUHBURST;
-  logic [1:0]                    IFUHTRANS;
-  logic [2:0]                    IFUHSIZE;
-  logic                          IFUHWRITE;
-  logic                          IFUHREADY;
-  
-  // AHB LSU interface
-  logic [PA_BITS-1:0]            LSUHADDR;
-  logic [XLEN-1:0]               LSUHWDATA;
-  logic [XLEN/8-1:0]             LSUHWSTRB;
-  logic                          LSUHWRITE;
-  logic                          LSUHREADY;
-  
-  logic                          BPPredWrongE, BPPredWrongM;
-  logic                          DirPredictionWrongM;
-  logic                          BTBPredPCWrongM;
-  logic                          RASPredPCWrongM;
-  logic                          PredictionInstrClassWrongM;
-  logic [3:0]                    InstrClassM;
-  logic                          InstrAccessFaultF, HPTWInstrAccessFaultM;
-  logic [2:0]                    LSUHSIZE;
-  logic [2:0]                    LSUHBURST;
-  logic [1:0]                    LSUHTRANS;
-  
-  logic                          DCacheMiss;
-  logic                          DCacheAccess;
-  logic                          ICacheMiss;
-  logic                          ICacheAccess;
-  logic                          BreakpointFaultM, EcallFaultM;
-  logic                          InstrDAPageFaultF;
-  logic                          BigEndianM;
-  logic                          FCvtIntE;
-  logic                          CommittedF;
-  logic 						 JumpOrTakenBranchM;
-  
-  // instruction fetch unit: PC, branch prediction, instruction cache
-  ifu ifu(.clk, .reset,
-    .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-    // Fetch
-    .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
-    .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
-    .ICacheAccess, .ICacheMiss,
-    // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,  .BPPredWrongM, 
-    // Mem
-    .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
-    .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
-    // Faults out
-    .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
-    // mmu management
-    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
-    .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
-    // pmp/pma (inside mmu) signals. 
-    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); 
-    
-  // integer execution unit: integer register file, datapath and controller
-  ieu ieu(.clk, .reset,
-     // Decode Stage interface
-     .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
-     // Execute Stage interface
-     .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, 
-     // Memory stage interface
-     .SquashSCW, // from LSU
-     .MemRWM, // read/write control goes to LSU
-     .AtomicM, // atomic control goes to LSU
-     .WriteDataM, // Write data to LSU
-     .Funct3M, // size and signedness to LSU
-     .SrcAM, // to privilege and fpu
-     .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
-     // Writeback stage
-     .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
-     .InstrValidM, .FCvtIntResW, .FCvtIntW,
-     // hazards
-     .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-     .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
-     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); 
-
-  lsu lsu(
-    .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
-    // CPU interface
-    .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
-    .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,            
-    .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
-    .ReadDataW, .FlushDCacheM,
-    // connected to ahb (all stay the same)
-    .LSUHADDR,  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, 
-    .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
-    // connect to csr or privilege and stay the same.
-    .PrivilegeModeW, .BigEndianM,          // connects to csr
-    .PMPCFG_ARRAY_REGW,     // connects to csr
-    .PMPADDR_ARRAY_REGW,    // connects to csr
-    // hptw keep i/o
-    .SATP_REGW, // from csr
-    .STATUS_MXR, // from csr
-    .STATUS_SUM,  // from csr
-    .STATUS_MPRV,  // from csr            
-    .STATUS_MPP,  // from csr      
-    .sfencevmaM,                   // connects to privilege
-    .LoadPageFaultM,   // connects to privilege
-    .StoreAmoPageFaultM, // connects to privilege
-    .LoadMisalignedFaultM, // connects to privilege
-    .LoadAccessFaultM,         // connects to privilege
-    .HPTWInstrAccessFaultM,         // connects to privilege
-    .StoreAmoMisalignedFaultM, // connects to privilege
-    .StoreAmoAccessFaultM,     // connects to privilege
-    .InstrDAPageFaultF,
-    .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
-    .LSUStallM);                    
-
-  if(BUS_SUPPORTED) begin : ebu
-    ebu ebu(// IFU connections
-      .clk, .reset,
-      // IFU interface
-      .IFUHADDR,
-      .IFUHBURST, 
-      .IFUHTRANS, 
-      .IFUHREADY,
-      .IFUHSIZE,
-      // LSU interface
-      .LSUHADDR,
-      .LSUHWDATA,
-      .LSUHWSTRB,
-      .LSUHSIZE,
-      .LSUHBURST,
-      .LSUHTRANS,
-      .LSUHWRITE,
-      .LSUHREADY,
-      // BUS interface
-      .HREADY, .HRESP, .HCLK, .HRESETn,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
-      .HPROT, .HTRANS, .HMASTLOCK);
-  end
-
-  // global stall and flush control  
-  hazard  hzu(
-    .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
-    .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
-    .LSUStallM, .IFUStallF,
-    .FCvtIntStallD, .FPUStallD,
-    .DivBusyE, .FDivBusyE,
-    .EcallFaultM, .BreakpointFaultM,
-    .WFIStallM,
-    // Stall & flush outputs
-    .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushD, .FlushE, .FlushM, .FlushW);    
-
-  // privileged unit
-  if (ZICSR_SUPPORTED) begin:priv
-    privileged priv(
-      .clk, .reset,
-      .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
-      .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
-      .InstrM, .CSRReadValW, .UnalignedPCNextF,
-      .RetM, .TrapM, .sfencevmaM,
-      .InstrValidM, .CommittedM, .CommittedF,
-      .FRegWriteM, .LoadStallD,
-      .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM,
-      .RASPredPCWrongM, .PredictionInstrClassWrongM,
-      .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
-      .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
-      .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, 
-      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
-      .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
-      .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
-      .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
-      .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
-      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
-      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
-  end else begin
-    assign CSRReadValW = 0;
-    assign UnalignedPCNextF = PCNext2F;
-    assign RetM = 0;
-    assign TrapM = 0;
-    assign WFIStallM = 0;
-    assign sfencevmaM = 0;
-    assign BigEndianM = 0;
-  end
-
-  // multiply/divide unit
-  if (M_SUPPORTED) begin:mdu
-    mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
-      .ForwardedSrcAE, .ForwardedSrcBE, 
-      .Funct3E, .Funct3M, .IntDivE, .W64E,
-      .MDUResultW, .DivBusyE); 
-  end else begin // no M instructions supported
-    assign MDUResultW = 0; 
-    assign DivBusyE = 0;
-  end
-
-  // floating point unit
-  if (F_SUPPORTED) begin:fpu
-    fpu fpu(
-      .clk, .reset,
-      .FRM_REGW, // Rounding mode from CSR
-      .InstrD, // instruction from IFU
-      .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
-      .ForwardedSrcAE, // Integer input being processed (from IEU)
-      .StallE, .StallM, .StallW, // stall signals from HZU
-      .FlushE, .FlushM, .FlushW, // flush signals from HZU
-      .RdE, .RdM, .RdW, // which FP register to write to (from IEU)
-      .STATUS_FS, // is floating-point enabled?
-      .FRegWriteM, // FP register write enable
-      .FpLoadStoreM,
-      .ForwardedSrcBE, // Integer input for intdiv
-      .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
-      .FPUStallD, // Stall the decode stage
-      .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
-      .FWriteDataM, // Data to be written to memory
-      .FIntResM, // data to be written to integer register
-      .FCvtIntResW, // fp -> int conversion result to be stored in int register
-      .FCvtIntW,   // fpu result selection
-      .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
-      .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
-      .SetFflagsM,        // FPU flags (to privileged unit)
-      .FIntDivResultW); 
-  end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-    assign FPUStallD = 0;
-    assign FWriteIntE = 0; 
-    assign FCvtIntE = 0;
-    assign FIntResM = 0;
-    assign FCvtIntW = 0;
-    assign FDivBusyE = 0;
-    assign IllegalFPUInstrM = 1;
-    assign SetFflagsM = 0;
-    assign FpLoadStoreM = 0;
-  end
-  
-endmodule
diff --git a/wallypipelinedsoc.sv b/wallypipelinedsoc.sv
deleted file mode 100644
index e792f6f89..000000000
--- a/wallypipelinedsoc.sv
+++ /dev/null
@@ -1,92 +0,0 @@
-///////////////////////////////////////////
-// wally-pipelinedsoc.sv
-//
-// Written: David_Harris@hmc.edu 6 November 2020
-// Modified: 
-//
-// Purpose: System on chip including pipelined processor and uncore memories/peripherals
-//
-// Documentation: RISC-V System on Chip Design (Figure 6.20)
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-import cvw::*;  // global CORE-V-Wally parameters
-
-module wallypipelinedsoc (
-  input  logic 		            clk, 
-  input  logic                reset_ext,        // external asynchronous reset pin
-  output logic                reset,            // reset synchronized to clk to prevent races on release
-  // AHB Interface
-  input  logic [AHBW-1:0]     HRDATAEXT,
-  input  logic 		            HREADYEXT, HRESPEXT,
-  output logic 		            HSELEXT,
-  // outputs to external memory, shared with uncore memory
-  output logic 		            HCLK, HRESETn,
-  output logic [PA_BITS-1:0]  HADDR,
-  output logic [AHBW-1:0]     HWDATA,
-  output logic [XLEN/8-1:0]   HWSTRB,
-  output logic 		            HWRITE,
-  output logic [2:0] 	        HSIZE,
-  output logic [2:0] 	        HBURST,
-  output logic [3:0] 	        HPROT,
-  output logic [1:0] 	        HTRANS,
-  output logic 		            HMASTLOCK,
-  output logic 		            HREADY,
-  // I/O Interface
-  input  logic                TIMECLK,          // optional for CLINT MTIME counter
-  input  logic [31:0] 	      GPIOPinsIn,       // inputs from GPIO
-  output logic [31:0] 	      GPIOPinsOut,      // output values for GPIO
-  output logic [31:0]         GPIOPinsEn,       // output enables for GPIO
-  input  logic 		            UARTSin,          // UART serial data input
-  output logic 		            UARTSout,         // UART serial data output
-  input  logic 		            SDCCmdIn,         // SDC Command input
-  output logic 		            SDCCmdOut,        // SDC Command output
-  output logic 		            SDCCmdOE,			    // SDC Command output enable
-  input  logic [3:0] 	        SDCDatIn,         // SDC data input
-  output logic 		            SDCCLK			      // SDC clock
-);
-
-  // Uncore signals
-  logic [AHBW-1:0]            HRDATA;           // from AHB mux in uncore
-  logic                       HRESP;            // response from AHB
-  logic                       MTimerInt, MSwInt; // timer and software interrupts from CLINT
-  logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
-  logic                       MExtInt,SExtInt;  // from PLIC
-
-  // synchronize reset to SOC clock domain
-  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
-   
-  // instantiate processor and internal memories
-  wallypipelinedcore core(.clk, .reset,
-    .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
-    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
-   );
-
-  // instantiate uncore if a bus interface exists
-  if (BUS_SUPPORTED) begin : uncore
-    uncore uncore(.HCLK, .HRESETn, .TIMECLK,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
-      .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
-      .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, 
-	    .UARTSout, .MTIME_CLINT, 
-	    .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
-  end
-
-endmodule