From 7b58683d2d0ed73bfa2e40f5b6270f91382740f9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Feb 2023 06:39:10 -0800 Subject: [PATCH 01/30] Commented config mode of synthesis makefile --- synthDC/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/synthDC/Makefile b/synthDC/Makefile index 76531d950..118536bf6 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -84,6 +84,14 @@ endif endif # adjust config if synthesizing with any modifications +# This code is subtle with ifneq. It successively turns off a larger +# set of features in order of cycle time limiting. +# When mod = orig, all features are ON +# When mod = PMP0, the number of PMP entries is set to 0 +# when mod = noPriv, the privileged unit and PMP are disabled +# when mod = noFPU, the FPU, privileged unit, and PMP are disabled +# when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled. + ifneq ($(MOD), orig) # PMP 0 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh From 2b80004db40eedd18bdd50be9b947255dd1b064a Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Feb 2023 06:42:38 -0800 Subject: [PATCH 02/30] Debug test case update --- tests/custom/debug/debug.S | 39 ++++++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S index 5be3c2012..e6e00e865 100644 --- a/tests/custom/debug/debug.S +++ b/tests/custom/debug/debug.S @@ -5,23 +5,38 @@ .global rvtest_entry_point rvtest_entry_point: - lui t0, 0x1e # turn on Floating point and XS + lui t0, 0x02 # turn on Floating point and XS csrs mstatus, t0 - # openhwgroup/cvw Issue #55 la a6, begin_signature la a7, rvtest_data - fadd.d ft0, ft1, ft2 + + # openhwgroup/cvw Issue #55 fld f4, 0(a7) fld f9, 8(a7) -# li x1, 0x7ff0000000000001 -# sd x1, 0(a6) -# fmv.w.x f4, x1 -# li x1, 0x7ff8000000000000 - # fmv.w.x f9, x1 - fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000 + fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000, hdl has been giving fff8000000000000 fsd f12, 0(a6) + # openhwgroup/cvw Issue #56 + fld f4, 16(a7) + fld f14, 24(a7) + fsgnjx.s f10,f4,f14 # expected f 0xffffffff7fc00000, hdl has been giving 0xcfa695b1047553b1 + fsd f19, 8(a6) + + # openhwgroup/cvw Issue #57 + fld f0, 32(a7) + fld f15, 40(a7) + fsgnjx.s f30,f0,f15 # expected f 0xfffffffffb3754ef, hdl has been giving 0xffffffff7b3754ef + fsd f30, 16(a6) + + # openhwgroup/cvw Issue #58 + fld f14, 48(a7) + fclass.s x2, f14 # expected 0x0000000000000200, hdl had been giving 0x0000000000000220 + sd x2, 24(a6) + + # fsgnjx.s, fclass.s, fsgnjn.s, fsgnj.s, fneg.s, fabs.s, fmv.s all treat inputs as dp rather than sp + + ######################### # HTIF and signature ######################### @@ -47,10 +62,14 @@ fromhost: rvtest_data: .dword 0x7ff0000000000001 .dword 0x7ff8000000000000 +.dword 0xcfa695b1047553b1 +.dword 0xffffffff7fc00000 +.dword 0xfffffffffb3754ef +.dword 0x7fefffffffffffff .EQU XLEN,64 begin_signature: - .fill 2*(XLEN/32),4,0xdeadbeef # + .fill 8*(XLEN/32),4,0xdeadbeef # end_signature: # Initialize stack with room for 512 bytes From d92f0e96424e8e7fb4702fe7a4d3dc3ec6966861 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Feb 2023 06:43:00 -0800 Subject: [PATCH 03/30] Ignore new tests from lab --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index 2d1454e3c..acaab4b01 100644 --- a/.gitignore +++ b/.gitignore @@ -101,3 +101,6 @@ sim/branch.log /fpga/generator/sim/syn-funcsim.v external sim/results +tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S +tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag + From 5b370bdc0f64ce8e2b0a64e23bc6f5335bfaeb60 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 16 Feb 2023 07:37:12 -0800 Subject: [PATCH 04/30] Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass. --- config/buildroot/wally-config.vh | 3 +- config/fpga/wally-config.vh | 1 + config/rv32e/wally-config.vh | 1 + config/rv32gc/wally-config.vh | 1 + config/rv32i/wally-config.vh | 1 + config/rv32imc/wally-config.vh | 1 + config/rv64fpquad/wally-config.vh | 1 + config/rv64gc/wally-config.vh | 1 + config/rv64i/wally-config.vh | 1 + src/privileged/csr.sv | 10 +++--- src/privileged/csri.sv | 18 +++++++--- src/privileged/csrs.sv | 57 ++++++++++++++++++++++++------- src/privileged/csrsr.sv | 2 +- 13 files changed, 76 insertions(+), 22 deletions(-) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index 783b9d91b..f10e11f99 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -40,8 +40,9 @@ `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 `define COUNTERS 32 +`define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 1 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index c4d9cf629..d0299c4e3 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -43,6 +43,7 @@ `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 `define COUNTERS 32 +`define SSTC_SUPPORTED 1 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh index 24242b384..8cd9ca3f4 100644 --- a/config/rv32e/wally-config.vh +++ b/config/rv32e/wally-config.vh @@ -44,6 +44,7 @@ `define COUNTERS 0 `define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index 089a9ada4..e45c2b093 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -43,6 +43,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index 0a081b415..d400cebe9 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -44,6 +44,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 0 diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh index b4293dcc6..010b6599f 100644 --- a/config/rv32imc/wally-config.vh +++ b/config/rv32imc/wally-config.vh @@ -43,6 +43,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh index 3757175a3..23a9aa05e 100644 --- a/config/rv64fpquad/wally-config.vh +++ b/config/rv64fpquad/wally-config.vh @@ -44,6 +44,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 1 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index c3dd87295..0b8a932d6 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -44,6 +44,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 90d7b4045..627cac8f7 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -44,6 +44,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 +`define SSTC_SUPPORTED 0 // LSU microarchitectural Features `define BUS_SUPPORTED 0 diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index ef4d73cb2..7b765bae0 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -113,6 +113,7 @@ module csr #(parameter logic SelMtvecM; logic [`XLEN-1:0] TVecAlignedM; logic InstrValidNotFlushedM; + logic STimerInt; // only valid unflushed instructions can access CSRs assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW; @@ -201,7 +202,7 @@ module csr #(parameter csri csri(.clk, .reset, .InstrValidNotFlushedM, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, - .MExtInt, .SExtInt, .MTimerInt, .MSwInt, + .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); csrsr csrsr(.clk, .reset, .StallW, @@ -227,11 +228,12 @@ module csr #(parameter csrs csrs(.clk, .reset, .InstrValidNotFlushedM, .CSRSWriteM, .STrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, - .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, + .STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]), + .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, - .WriteSSTATUSM, .IllegalCSRSAccessM); + .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, + .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt); end else begin assign WriteSSTATUSM = 0; assign CSRSReadValM = 0; diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index 0de65beed..bdbb0f591 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -39,13 +39,14 @@ module csri #(parameter input logic CSRMWriteM, CSRSWriteM, input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, - input logic MExtInt, SExtInt, MTimerInt, MSwInt, + input logic MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt, output logic [11:0] MIP_REGW, MIE_REGW, - output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 + output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; + logic STIP; // Interrupt Write Enables assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM; @@ -58,7 +59,13 @@ module csri #(parameter // SEIP, STIP, SSIP is writable in MIP if S mode exists // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask - assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) + if (`SSTC_SUPPORTED) begin + assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec) + assign STIP = STimerInt; + end else begin + assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) + assign STIP = MIP_REGW_writeable[5]; + end assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask @@ -75,5 +82,8 @@ module csri #(parameter else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields - assign MIP_REGW = {MExtInt,1'b0,SExtInt|MIP_REGW_writeable[9],1'b0,MTimerInt,1'b0,MIP_REGW_writeable[5],1'b0,MSwInt,1'b0,MIP_REGW_writeable[1],1'b0}; + + assign MIP_REGW = {MExtInt, 1'b0, SExtInt|MIP_REGW_writeable[9], 1'b0, + MTimerInt, 1'b0, STIP, 1'b0, + MSwInt, 1'b0, MIP_REGW_writeable[1], 1'b0}; endmodule diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 3dfb2cbea..99c56ad1b 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -41,22 +41,27 @@ module csrs #(parameter SCAUSE = 12'h142, STVAL = 12'h143, SIP= 12'h144, + STIMECMP = 12'h14D, + STIMECMPH = 12'h15D, SATP = 12'h180) ( - input logic clk, reset, - input logic InstrValidNotFlushedM, - input logic CSRSWriteM, STrapM, - input logic [11:0] CSRAdrM, - input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, - input logic STATUS_TVM, - input logic [`XLEN-1:0] CSRWriteValM, - input logic [1:0] PrivilegeModeW, + input logic clk, reset, + input logic InstrValidNotFlushedM, + input logic CSRSWriteM, STrapM, + input logic [11:0] CSRAdrM, + input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, + input logic STATUS_TVM, + input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear + input logic [`XLEN-1:0] CSRWriteValM, + input logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW, output logic [`XLEN-1:0] SEPC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SATP_REGW, - input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, - output logic WriteSSTATUSM, - output logic IllegalCSRSAccessM + input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, + input logic [63:0] MTIME_CLINT, + output logic WriteSSTATUSM, + output logic IllegalCSRSAccessM, + output logic STimerInt ); // Constants @@ -66,10 +71,13 @@ module csrs #(parameter logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; + logic WriteSTIMECMPM, WriteSTIMECMPHM; logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; logic [`XLEN-1:0] SCAUSE_REGW; + logic [63:0] STIMECMP_REGW; // write enables + // *** can InstrValidNotFlushed be factored out of all these writes into CSRWriteM? assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; @@ -78,6 +86,8 @@ module csrs #(parameter assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM; assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM; assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM; + assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & MCOUNTEREN_TM & InstrValidNotFlushedM; + assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & MCOUNTEREN_TM & (`XLEN == 32) & InstrValidNotFlushedM; // CSRs flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); @@ -90,7 +100,20 @@ module csrs #(parameter else assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); + if (`XLEN == 64) + flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW); + else begin + flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]); + flopenr #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]); + end + // Supervisor timer interrupt logic + // Spec is a bit peculiar - Machine timer interrupts are produced in CLINT, while Supervisor timer interrupts are in CSRs + if (`SSTC_SUPPORTED) + assign STimerInt = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison + else + assign STimerInt = 0; + // CSR Reads always_comb begin:csrr IllegalCSRSAccessM = 0; @@ -109,10 +132,20 @@ module csrs #(parameter if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1; end SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW}; + STIMECMP: if (MCOUNTEREN_TM) CSRSReadValM = STIMECMP_REGW[`XLEN-1:0]; + else begin + CSRSReadValM = 0; + IllegalCSRSAccessM = 1; + end + STIMECMPH: if (MCOUNTEREN_TM & (`XLEN == 32)) CSRSReadValM[31:0] = STIMECMP_REGW[63:32]; + else begin // not supported for RV64 + CSRSReadValM = 0; + IllegalCSRSAccessM = 1; + end default: begin CSRSReadValM = 0; IllegalCSRSAccessM = 1; - end + end endcase end endmodule diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 1fa1fe8e7..a92aca3be 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -68,7 +68,7 @@ module csrsr ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; - assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. + assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, From b0cedcff7cbabf4ae675a3c2241fb8e88789c1b3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 16 Feb 2023 07:37:44 -0800 Subject: [PATCH 05/30] Added check that SSTC_SUPPORTED is viable --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 329d4c605..9c3e0cf0c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -554,9 +554,9 @@ module riscvassertions; assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); + assert (`SSTC_SUPPORTED == 0 | (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); end - // *** DH 8/23/ endmodule From 68defb99e7e9b580a364ac0882e4196f119797b0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 16 Feb 2023 08:25:23 -0800 Subject: [PATCH 06/30] Fix DC setup typos --- synthDC/.synopsys_dc.setup | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 1310c4dd7..26431bf91 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -20,15 +20,14 @@ if {$tech == "sky130"} { } elseif {$tech == "tsmc28"} { set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a lappend search_path $s10lib -} -elseif {$tech == "tsmc28psyn"} { +} elseif {$tech == "tsmc28psyn"} { set TLU /home/jstine/TLU+ set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a lappend search_path $s10lib set TLUPLUS true set mw_logic1_net VDD set mw_logic0_net VSS - set TLU_PDK /import/yukari1/jstine/TLU+/ + set TLU_PDK /home/jstine/TLU+/ set CAPTABLE $TLU/1p8m/ set MW_REFERENCE_LIBRARY /home/jstine/MW set MW_TECH_FILE tcbn28hpcplusbwp7t30p140 @@ -50,7 +49,6 @@ if {$tech == "sky130"} { lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db } elseif {$tech == "tsmc28"} { lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db -} } elseif {$tech == "tsmc28psyn"} { set mw_reference_library [list ] lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db From 3591fd5aea7c71fc0440e13e7c01fb80049fd7e9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 16 Feb 2023 11:55:23 -0800 Subject: [PATCH 07/30] corrections to DC setup --- synthDC/.synopsys_dc.setup | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 26431bf91..90ea5c171 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -52,7 +52,7 @@ if {$tech == "sky130"} { } elseif {$tech == "tsmc28psyn"} { set mw_reference_library [list ] lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db - lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140 + lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140 } # Set Link Library From 43afa343387c5f639b86246f93d88a2356b2c780 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 16 Feb 2023 17:52:25 -0800 Subject: [PATCH 08/30] Update alu.sv --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index ccd55779c..3f25e6de7 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -68,7 +68,7 @@ module alu #(parameter WIDTH=32) ( // SLT assign SLT = {{(WIDTH-1){1'b0}}, LT}; - assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; + assign SLTU = {{(WIDTH-1){1'b0}}, LT}; // Select appropriate ALU Result always_comb From 113b12472122c818d49389f3ae84e342b2aa90c8 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 16 Feb 2023 17:52:44 -0800 Subject: [PATCH 09/30] Update controller.sv --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d66425343..cafe7d3d4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -99,7 +99,7 @@ module controller( logic CSRWriteD, CSRWriteE; // CSR write logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ - logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals + logic ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken From 33eb5423cb87e904ac27b155ef660a6b0a93d6de Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 16 Feb 2023 17:53:31 -0800 Subject: [PATCH 10/30] Update datapath.sv --- src/ieu/datapath.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 60d43de92..07bd4faef 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -101,7 +101,7 @@ module datapath ( flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E); flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); - flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); + flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs1E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE); From 59cb560e0109ca6853fe96a4ebf940e048aaa215 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 16 Feb 2023 17:54:27 -0800 Subject: [PATCH 11/30] Update testbench.sv --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 329d4c605..073b02e5b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -281,7 +281,7 @@ logic [3:0] dummy; // once the test inidicates it's done we need to immediately hold reset for a number of cycles. if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1; else begin // hit reset threshold so we remove reset. - InReset = 0; + //InReset = 0; ResetCount = 0; end end else begin From 0eb0817ea1d9bb145774992ffa902f2e9e5f603d Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 16 Feb 2023 17:55:46 -0800 Subject: [PATCH 12/30] Update testbench.sv --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 073b02e5b..28e58bfb0 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -281,7 +281,7 @@ logic [3:0] dummy; // once the test inidicates it's done we need to immediately hold reset for a number of cycles. if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1; else begin // hit reset threshold so we remove reset. - //InReset = 0; + //InReset = 0; hmmm-I smell a wumpus ResetCount = 0; end end else begin From 0d2baed94343332322c0468dcb89dd0012ca2310 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 16 Feb 2023 18:10:05 -0800 Subject: [PATCH 13/30] Reverted lab3 changes in dev branch --- src/ieu/alu.sv | 2 +- src/ieu/controller.sv | 2 +- src/ieu/datapath.sv | 2 +- testbench/testbench.sv | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3f25e6de7..ccd55779c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -68,7 +68,7 @@ module alu #(parameter WIDTH=32) ( // SLT assign SLT = {{(WIDTH-1){1'b0}}, LT}; - assign SLTU = {{(WIDTH-1){1'b0}}, LT}; + assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; // Select appropriate ALU Result always_comb diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index cafe7d3d4..d66425343 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -99,7 +99,7 @@ module controller( logic CSRWriteD, CSRWriteE; // CSR write logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ - logic ControlsD; // Main Instruction Decoder control signals + logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 07bd4faef..60d43de92 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -101,7 +101,7 @@ module datapath ( flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E); flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); - flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs1E); + flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b90464521..61143b121 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -281,7 +281,7 @@ logic [3:0] dummy; // once the test inidicates it's done we need to immediately hold reset for a number of cycles. if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1; else begin // hit reset threshold so we remove reset. - //InReset = 0; hmmm-I smell a wumpus + InReset = 0; ResetCount = 0; end end else begin From 9d83749ca62cd4370bbb7f5768acdab92c36df34 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 16 Feb 2023 19:40:27 -0800 Subject: [PATCH 14/30] moved riscvassertons to its own file, added proper license headers to testbench support files --- testbench/common/functionName.sv | 33 ++++++--------- testbench/common/instrNameDecTB.sv | 23 +++++++++++ testbench/common/instrTrackerTB.sv | 21 ++++++++++ testbench/common/riscvassertions.sv | 64 +++++++++++++++++++++++++++++ testbench/common/wallyTracer.sv | 28 ++++++++++++- testbench/testbench.sv | 41 ------------------ testbench/testbench_imperas.sv | 40 ------------------ 7 files changed, 147 insertions(+), 103 deletions(-) create mode 100644 testbench/common/riscvassertions.sv diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index f3cb656f5..17b27ec5d 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -1,33 +1,24 @@ /////////////////////////////////////////// -// datapath.sv +// functionName.sv // -// Written: Ross Thompson -// email: ross1728@gmail.com -// Created: November 9, 2019 -// Modified: March 04, 2021 -// -// Purpose: Finds the current function or global assembly label based on PCE. +// Purpose: decode name of function // // A component of the Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index 4c1a68502..dd993e715 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -1,3 +1,26 @@ +/////////////////////////////////////////// +// instrNameDecTB.sv +// +// Purpose: decode name of function +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + // decode the instruction name, to help the test bench module instrNameDecTB( input logic [31:0] instr, diff --git a/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv index 2b0ca7c50..429ff8489 100644 --- a/testbench/common/instrTrackerTB.sv +++ b/testbench/common/instrTrackerTB.sv @@ -1,3 +1,24 @@ +/////////////////////////////////////////// +// instrTrackerTB.sv +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + module instrTrackerTB( input logic clk, reset, FlushE, input logic [31:0] InstrF, InstrD, diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv new file mode 100644 index 000000000..f6cb4c6f6 --- /dev/null +++ b/testbench/common/riscvassertions.sv @@ -0,0 +1,64 @@ +/////////////////////////////////////////// +// riscvassertions.sv +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module riscvassertions; + initial begin + assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); + assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); + assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); + assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); + assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); + assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); + assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); + assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); + assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); + assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); + assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); + assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); + assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); + assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); + assert (`SSTC_SUPPORTED == 0 | (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); + end + +endmodule + + diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 14b229685..6911ddb56 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -1,3 +1,24 @@ +/////////////////////////////////////////// +// wallyTracer.sv +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + `include "wally-config.vh" `define NUM_REGS 32 @@ -14,7 +35,12 @@ module wallyTracer(rvviTrace rvvi); // wally specific signals logic reset; - + + logic clk; + logic InstrValidD, InstrValidE; + logic StallF, StallD; + logic STATUS_SXL, STATUS_UXL; + logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic InstrValidM, InstrValidW; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 61143b121..6b4d8bb86 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -519,47 +519,6 @@ logic [3:0] dummy; endmodule -module riscvassertions; - initial begin - assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); - assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); - assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); - assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); - assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); - assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); - assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); - assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); - assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - assert (`SSTC_SUPPORTED == 0 | (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); - end - -endmodule - - /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */ diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index c7d987b83..d760bf5bc 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -322,46 +322,6 @@ module testbench; endmodule -module riscvassertions; - initial begin - assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); - assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); - assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); - assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); - assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); - assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); - assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); - assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally."); - assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - end - - // *** DH 8/23/ -endmodule - /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */ From db3ebaf38a294c05309af917161aaadad11b48a4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 10:35:39 -0800 Subject: [PATCH 15/30] fixed various sweep options to not run an extra job --- synthDC/wallySynth.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index d89964c10..426f4a12d 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -48,12 +48,12 @@ if __name__ == '__main__': config = args.version if args.version else 'rv32e' for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep runSynth(config, mod, tech, freq, maxopt, usesram, usetopo) - if args.configsweep: + elif args.configsweep: defaultfreq = 1500 if tech == 'sky90' else 5000 freq = args.targetfreq if args.targetfreq else defaultfreq for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs runSynth(config, mod, tech, freq, maxopt, usesram, usetopo) - if args.featuresweep: + elif args.featuresweep: defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' From 02a1b77b9ded377e620a3e77083980687f9098dc Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 10:52:17 -0800 Subject: [PATCH 16/30] Fixing loads and wire loading for physical synthesis. Also put Milkyway library in each run directory so they don't conflict across runs --- synthDC/scripts/synth.tcl | 34 +++++++++++++++++++--------------- synthDC/wallySynth.py | 1 + 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 830203520..fe1e31fac 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -54,18 +54,20 @@ set MY_LIB_NAME $my_toplevel # Create MW if { [shell_is_in_topographical_mode] } { echo "In Topographical Mode...processing\n" - if {[file isdirectory $MY_LIB_NAME]} { - echo "MW directory already here, deleting/readdding." - [exec rm -rf $my_toplevel] - create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ - -mw_reference_library $mw_reference_library $MY_LIB_NAME - } else { - create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ - -mw_reference_library $mw_reference_library $MY_LIB_NAME - } + create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ + -mw_reference_library $mw_reference_library $outputDir/$MY_LIB_NAME +# if {[file isdirectory $MY_LIB_NAME]} { + #echo "MW directory already here, deleting/reading." + #[exec rm -rf $my_toplevel] +# create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ +# -mw_reference_library $mw_reference_library $MY_LIB_NAME +# } else { +# create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ +# -mw_reference_library $mw_reference_library $MY_LIB_NAME +# } # Open MW - open_mw_lib $MY_LIB_NAME + open_mw_lib $outputDir/$MY_LIB_NAME # TLU+ set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \ @@ -73,7 +75,7 @@ if { [shell_is_in_topographical_mode] } { } else { if {[file isdirectory $MY_LIB_NAME]} { - [exec rm -rf $my_toplevel] + [exec rm -rf $my_toplevel] echo "MW directory already here, deleting." } echo "In normal DC mode...processing\n" @@ -152,7 +154,7 @@ if {$tech == "sky130"} { } elseif {$drive == "FLOP"} { set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk } -} elseif {$tech == "tsmc28"} { +} elseif {$tech == "tsmc28" || $tech="tsmc28psyn"} { if {$drive == "INV"} { set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk } elseif {$drive == "FLOP"} { @@ -178,7 +180,7 @@ if {$tech == "sky130"} { } elseif {$drive == "FLOP"} { set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] } -} elseif {$tech == "tsmc28"} { +} elseif {$tech == "tsmc28" || $tech = "tsmc28psyn"} { if {$drive == "INV"} { set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] } elseif {$drive == "FLOP"} { @@ -186,8 +188,10 @@ if {$tech == "sky130"} { } } -# Set the wire load model -set_wire_load_mode "top" +if ($tech != "tsmc28psyn") { + # Set the wire load model + set_wire_load_mode "top" +} # Set switching activities # default activity factors are 1 for clocks, 0.1 for others diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 426f4a12d..e2918620a 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -19,6 +19,7 @@ if __name__ == '__main__': techs = ['sky90', 'tsmc28', 'tsmc28psyn'] allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] + freqVaryPct = [0, 10] pool = Pool() From 6c6c56e10238f46d7845fe7ab88b53c9cf2967d0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 10:59:31 -0800 Subject: [PATCH 17/30] Fixed TLU corners --- synthDC/.synopsys_dc.setup | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index ccc0c67c8..15367d707 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -32,8 +32,8 @@ if {$tech == "sky130"} { set CAPTABLE $TLU/1p8m/ set MW_REFERENCE_LIBRARY /home/jstine/MW set MW_TECH_FILE tcbn28hpcplusbwp30p140 - set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus - set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus + set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus + set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map } From 2c762fd479c16b3d352b52f089a116abe1016b43 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 11:00:00 -0800 Subject: [PATCH 18/30] sweep debugging --- synthDC/scripts/synth.tcl | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index fe1e31fac..c4579e5c5 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -56,16 +56,6 @@ if { [shell_is_in_topographical_mode] } { echo "In Topographical Mode...processing\n" create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ -mw_reference_library $mw_reference_library $outputDir/$MY_LIB_NAME -# if {[file isdirectory $MY_LIB_NAME]} { - #echo "MW directory already here, deleting/reading." - #[exec rm -rf $my_toplevel] -# create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ -# -mw_reference_library $mw_reference_library $MY_LIB_NAME -# } else { -# create_mw_lib -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \ -# -mw_reference_library $mw_reference_library $MY_LIB_NAME -# } - # Open MW open_mw_lib $outputDir/$MY_LIB_NAME @@ -74,10 +64,6 @@ if { [shell_is_in_topographical_mode] } { -tech2itf_map $PRS_MAP_FILE } else { - if {[file isdirectory $MY_LIB_NAME]} { - [exec rm -rf $my_toplevel] - echo "MW directory already here, deleting." - } echo "In normal DC mode...processing\n" } @@ -154,7 +140,7 @@ if {$tech == "sky130"} { } elseif {$drive == "FLOP"} { set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk } -} elseif {$tech == "tsmc28" || $tech="tsmc28psyn"} { +} elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} { if {$drive == "INV"} { set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk } elseif {$drive == "FLOP"} { @@ -180,7 +166,7 @@ if {$tech == "sky130"} { } elseif {$drive == "FLOP"} { set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] } -} elseif {$tech == "tsmc28" || $tech = "tsmc28psyn"} { +} elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} { if {$drive == "INV"} { set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] } elseif {$drive == "FLOP"} { @@ -188,7 +174,7 @@ if {$tech == "sky130"} { } } -if ($tech != "tsmc28psyn") { +if {$tech != "tsmc28psyn"} { # Set the wire load model set_wire_load_mode "top" } From aba29f6cc84282e4bd3ec31a507f1b6ca25e7e1a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 13:51:05 -0800 Subject: [PATCH 19/30] Synthesis with memories --- src/generic/mem/ram1p1rwbe.sv | 16 +++------------- src/generic/mem/ram1p1rwbe_64x128.sv | 3 ++- src/generic/mem/ram1p1rwbe_64x22.sv | 10 ++++++---- src/generic/mem/ram1p1rwbe_64x44.sv | 9 +++++---- src/generic/mem/ram2p1r1wbe.sv | 6 +++--- src/generic/mem/ram2p1r1wbe_1024x36.sv | 8 ++++++-- src/generic/mem/ram2p1r1wbe_1024x68.sv | 6 ++++-- src/generic/mem/ram2p1r1wbe_64x32.sv | 7 +++++-- src/generic/mem/rom1p1r.sv | 4 ++-- synthDC/.synopsys_dc.setup | 2 ++ synthDC/extractSummary.py | 14 +++++++------- synthDC/wallySynth.py | 2 +- 12 files changed, 46 insertions(+), 41 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index f1e784c13..7a7dadbed 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -49,7 +49,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 64) begin + if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -59,7 +59,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin + end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag genvar index; // 64 x 44-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -69,17 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin - genvar index; - // 64 x 128-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); - - end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin + end else if (`USE_SRAM == 1 & WIDTH == 22 & DEPTH == 32) begin // RV32 cache tag genvar index; // 64 x 22-bit SRAM logic [WIDTH-1:0] BitWriteMask; diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index fa8e32f0b..a28b64e9a 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -35,6 +35,7 @@ module ram1p1rwbe_64x128( ); // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor - generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + //generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + ts1n28hpcpsvtb64x128m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 84c8d1b75..8b04c7979 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -29,12 +29,14 @@ module ram1p1rwbe_64x22( input logic CEB, input logic WEB, input logic [5:0] A, - input logic [127:0] D, - input logic [127:0] BWEB, - output logic [127:0] Q + input logic [21:0] D, + input logic [21:0] BWEB, + output logic [21:0] Q ); // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor - generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + // use part of a larger RAM to avoid generating more flavors of RAM + ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); + //generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 7fa71f312..080dd9977 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -29,12 +29,13 @@ module ram1p1rwbe_64x44( input logic CEB, input logic WEB, input logic [5:0] A, - input logic [127:0] D, - input logic [127:0] BWEB, - output logic [127:0] Q + input logic [43:0] D, + input logic [43:0] BWEB, + output logic [43:0] Q ); // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor - generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + // generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index da099cdc7..d285dbe16 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( // TRUE Smem macro // *************************************************************************** - if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin + if (`USE_SRAM == 1 & WIDTH == 68 & DEPTH == 1024) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 & WIDTH == 36 & DEPTH == 1024) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -76,7 +76,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 & WIDTH == 2 & DEPTH == 1024) begin logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMWriteData; diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 0aad7db4a..7ceef23c0 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -42,7 +42,11 @@ module ram2p1r1wbe_1024x36( ); // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor - generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // use part of a larger RAM to avoid generating more flavors of RAM + tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA(DA[35:0]), .DB(DB[35:0]), + .BWEBA(BWEBA[35:0]), .BWEBB(BWEBB[35:0]), .QA(QA[35:0]), .QB(QB[35:0])); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index e6a6b6257..c6c0f01af 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -42,7 +42,9 @@ module ram2p1r1wbe_1024x68( ); // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor - generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 8bc19637d..da080b2cd 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -42,7 +42,10 @@ module ram2p1r1wbe_64x32( ); // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor - generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + tsdn28hpcpa64x32m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - endmodule diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 64cb9224b..c5c1f8b0a 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -38,10 +38,10 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // Core Memory logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; - if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin + if ((`USE_SRAM == 1) & (DATA_WIDTH == 64)) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); - end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin + end if ((`USE_SRAM == 1) & (DATA_WIDTH == 32)) begin rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); end else begin diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 15367d707..3c8b566a7 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -72,6 +72,8 @@ if {$tech == "tsmc28"} { lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db + lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db + lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db } # Set up User Information diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 3d939644a..5aeb5aa9f 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -103,7 +103,7 @@ def freqPlot(tech, width, config): freqs = freqsL[ind] freqs, delays, areas = noOutliers(median, freqs, delays, areas) - c = 'blue' if ind else 'green' + c = 'blue' if ind else 'gray' targs = [1000/f for f in freqs] ax1.scatter(targs, delays, color=c) @@ -113,7 +113,7 @@ def freqPlot(tech, width, config): delays = list(flatten(delaysL)) areas = list(flatten(areasL)) - legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + legend_elements = [lines.Line2D([0], [0], color='gray', ls='', marker='o', label='timing achieved'), lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] ax1.legend(handles=legend_elements) @@ -246,8 +246,8 @@ if __name__ == '__main__': TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy") techdict = {} - techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) - techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) + techdict['sky90'] = TechSpec('gray', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) + techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) current_directory = os.getcwd() final_directory = os.path.join(current_directory, 'wallyplots') @@ -256,10 +256,10 @@ if __name__ == '__main__': synthsintocsv() synthsfromcsv('Summary.csv') - freqPlot('tsmc28', 'rv32', 'e') + freqPlot('tsmc28psyn', 'rv32', 'e') freqPlot('sky90', 'rv32', 'e') plotFeatures('sky90', 'rv64', 'gc') - plotFeatures('tsmc28', 'rv64', 'gc') + plotFeatures('tsmc28psyn', 'rv64', 'gc') plotConfigs('sky90', mod='orig') - plotConfigs('tsmc28', mod='orig') + plotConfigs('tsmc28psyn', mod='orig') normAreaDelay(mod='orig') diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index e2918620a..ef93da7fe 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -19,7 +19,7 @@ if __name__ == '__main__': techs = ['sky90', 'tsmc28', 'tsmc28psyn'] allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] - freqVaryPct = [0, 10] +# freqVaryPct = [-20, -10, 0, 10, 20] pool = Pool() From 3f2f48ddc6172dcfd80dc57b8f0610fbfd7179f2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 15:15:37 -0800 Subject: [PATCH 20/30] Continue fixing memory macros for synthesis --- src/generic/mem/ram1p1rwbe_64x128.sv | 2 +- src/generic/mem/ram1p1rwbe_64x22.sv | 2 +- src/generic/mem/ram1p1rwbe_64x44.sv | 2 +- src/generic/mem/ram2p1r1wbe_1024x36.sv | 2 +- src/generic/mem/ram2p1r1wbe_1024x68.sv | 2 +- src/generic/mem/ram2p1r1wbe_64x32.sv | 2 +- synthDC/.synopsys_dc.setup | 2 +- synthDC/extractSummary.py | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index a28b64e9a..84a3e74f9 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -36,6 +36,6 @@ module ram1p1rwbe_64x128( // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor //generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); - ts1n28hpcpsvtb64x128m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + TS1N28HPCPSVTB64X128M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 8b04c7979..3020e0fdf 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -36,7 +36,7 @@ module ram1p1rwbe_64x22( // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor // use part of a larger RAM to avoid generating more flavors of RAM - ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); + TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); //generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 080dd9977..89730a42b 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -36,6 +36,6 @@ module ram1p1rwbe_64x44( // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor // generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); - ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 7ceef23c0..aee2d0aab 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -45,7 +45,7 @@ module ram2p1r1wbe_1024x36( //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // use part of a larger RAM to avoid generating more flavors of RAM - tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA(DA[35:0]), .DB(DB[35:0]), .BWEBA(BWEBA[35:0]), .BWEBB(BWEBB[35:0]), .QA(QA[35:0]), .QB(QB[35:0])); diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index c6c0f01af..108530bee 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -44,7 +44,7 @@ module ram2p1r1wbe_1024x68( // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index da080b2cd..c18db670e 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -46,6 +46,6 @@ module ram2p1r1wbe_64x32( // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - tsdn28hpcpa64x32m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 3c8b566a7..c516fcf6f 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -67,7 +67,7 @@ set cache_read $cache_write lappend search_path ./scripts lappend search_path ./hdl lappend search_path ./mapped -if {$tech == "tsmc28"} { +if {$tech == "tsmc28" || $tech == "tsmc28psyn"} { set memory /home/jstine/WallyMem/rv64gc/ lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 5aeb5aa9f..85bc6f0aa 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -85,7 +85,7 @@ def freqPlot(tech, width, config): freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod): - ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + ind = (1000/oneSynth.delay < (0.95*oneSynth.freq)) # when delay is within target clock period freqsL[ind] += [oneSynth.freq] delaysL[ind] += [oneSynth.delay] areasL[ind] += [oneSynth.area] From daf2f822c279b293e04b84978457054823bdca3e Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 15:33:49 -0800 Subject: [PATCH 21/30] Memory synthesis updates --- src/generic/mem/ram1p1rwbe.sv | 2 +- src/generic/mem/ram1p1rwbe_64x22.sv | 2 +- src/generic/mem/ram2p1r1wbe_64x32.sv | 2 -- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 7a7dadbed..4c1707452 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( +module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 3020e0fdf..4df3bc47f 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -37,6 +37,6 @@ module ram1p1rwbe_64x22( // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor // use part of a larger RAM to avoid generating more flavors of RAM TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); - //generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + // genericRAM #(64, 22) sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index c18db670e..e551099f4 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -44,8 +44,6 @@ module ram2p1r1wbe_64x32( // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule From 239bb3abbc86dc7f8e23db7f13ca87239190d9c3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 17:37:05 -0800 Subject: [PATCH 22/30] Turned off default USE_SRAM in Makefile --- synthDC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index fbfb459ad..4f6b10a7b 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -20,7 +20,7 @@ export MAXCORES ?= 1 # The output netlist is hard to interpret, but significantly better PPA export MAXOPT ?= 0 export DRIVE ?= FLOP -export USESRAM ?= 1 +export USESRAM ?= 0 export USETOPO ?= 0 time := $(shell date +%F-%H-%M) From a6b65944bc718919b2d894acdbb0f83b21431e89 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 19:13:52 -0800 Subject: [PATCH 23/30] Listed more Python files for installation --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index d8c2432d4..757781024 100644 --- a/README.md +++ b/README.md @@ -209,6 +209,12 @@ It is most convenient if the sysadmin installs riscof into the server’s Python However, riscof can also be installed and run locally by individual users. +### Other Python libraries + +While a sysadmin is installing Python libraries, it's worth doing some more that will be needed by visualization scripts. + + $ sudo pip3 install matplotlib scipy sklearn adjustText lief + ### Install Verilator Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. From 154d7eb9ef2792a65d738b54ef7ea1cb3974f17d Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 19:14:38 -0800 Subject: [PATCH 24/30] Fixed RAM bugs and refactored with read taking place after clock edge rather than before. --- src/generic/mem/ram1p1rwbe.sv | 16 +++++++++++----- src/generic/mem/ram2p1r1wbe.sv | 17 +++++++++++------ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4c1707452..f3c98873e 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) ( +module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -69,7 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 & WIDTH == 22 & DEPTH == 32) begin // RV32 cache tag + end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag genvar index; // 64 x 22-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -86,9 +86,15 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) ( integer i; // Read - always_ff @(posedge clk) - if(ce) dout <= #1 RAM[addr]; - + logic [$clog2(DEPTH)-1:0] addrd; + flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd); + assign dout = RAM[addrd]; + + /* // Read + always_ff @(posedge clk) + if(ce) dout <= #1 mem[addr]; */ + + // Write divided into part for bytes and part for extra msbs // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. // Therefore these always blocks use the older always @(posedge clk) diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index d285dbe16..cefd5ab9f 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -33,7 +33,7 @@ `include "wally-config.vh" -module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( +module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, @@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( // TRUE Smem macro // *************************************************************************** - if (`USE_SRAM == 1 & WIDTH == 68 & DEPTH == 1024) begin + if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end else if (`USE_SRAM == 1 & WIDTH == 36 & DEPTH == 1024) begin + end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -76,7 +76,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end else if (`USE_SRAM == 1 & WIDTH == 2 & DEPTH == 1024) begin + end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMWriteData; @@ -113,9 +113,14 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** integer i; - // Read + // Read + logic [$clog2(DEPTH)-1:0] ra1d; + flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); + assign rd1 = mem[ra1d]; + +/* // Read always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; + if(ce1) rd1 <= #1 mem[ra1]; */ // Write divided into part for bytes and part for extra msbs if(WIDTH >= 8) From 2168113d60e0056c1c0072e4cb420da05dc95721 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 20:50:43 -0800 Subject: [PATCH 25/30] Fixed warnings when compiling wallyTracer --- testbench/common/wallyTracer.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 6911ddb56..6daf48e9d 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -35,12 +35,10 @@ module wallyTracer(rvviTrace rvvi); // wally specific signals logic reset; - logic clk; logic InstrValidD, InstrValidE; logic StallF, StallD; logic STATUS_SXL, STATUS_UXL; - logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic InstrValidM, InstrValidW; From 63a6567ed321385bc8f3adddccfd4646c5f82b83 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 20:51:43 -0800 Subject: [PATCH 26/30] Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55 --- src/fpu/fpu.sv | 32 +++++++++++++------------------- src/fpu/unpack.sv | 12 ++++++++---- src/fpu/unpackinput.sv | 37 +++++++++++++++++++++++++++++++++---- 3 files changed, 54 insertions(+), 27 deletions(-) diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 6abb76b0b..73bf1971e 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -110,6 +110,7 @@ module fpu ( logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage logic XExpMaxE; // is the exponent all ones (max value) + logic [`FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations // Fma Signals logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting @@ -200,23 +201,20 @@ module fpu ( mux3 #(`FLEN) fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE); // Select NAN-boxed value of Y = 1.0 in proper format for fma to add/subtract X*Y+Z - generate - if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}; - else if(`FPSIZES == 2) - mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes - else if(`FPSIZES == 3 | `FPSIZES == 4) - mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}, - {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}, - {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}, - {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes - endgenerate + if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}; + else if(`FPSIZES == 2) + mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes + else if(`FPSIZES == 3 | `FPSIZES == 4) + mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}, + {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}, + {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}, + {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); mux2 #(`FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z // For add and subtract, Z comes from second source operand - generate - if(`FPSIZES == 1) assign BoxedZeroE = 0; + if(`FPSIZES == 1) assign BoxedZeroE = 0; else if(`FPSIZES == 2) mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes else if(`FPSIZES == 3 | `FPSIZES == 4) @@ -224,7 +222,6 @@ module fpu ( {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}, {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes - endgenerate assign FmaZSelE = {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]}; mux3 #(`FLEN) fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE); @@ -234,7 +231,7 @@ module fpu ( .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), - .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE)); + .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE), .XPostBox(XPostBoxE)); // fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), @@ -255,7 +252,7 @@ module fpu ( .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE)); // sign injection: fsgnj/fsgnjx/fsgnjn - fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XE), .Fmt(FmtE), .SgnRes(SgnResE)); + fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XPostBoxE), .Fmt(FmtE), .SgnRes(SgnResE)); // classify: fclass fclassify fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE), @@ -268,7 +265,6 @@ module fpu ( // NaN Box SrcA to convert integer to requested FP size - generate if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}; else if(`FPSIZES == 2) mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); @@ -277,14 +273,12 @@ module fpu ( {{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]}, {{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes - endgenerate // select a result that may be written to the FP register mux3 #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE); assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE); // select the result that may be written to the integer register - to IEU - generate if(`FPSIZES == 1) assign SgnExtXE = XE; else if(`FPSIZES == 2) @@ -294,7 +288,7 @@ module fpu ( {{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]}, {{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]}, XE, FmtE, SgnExtXE); - endgenerate + if (`FLEN>`XLEN) assign IntSrcXE = SgnExtXE[`XLEN-1:0]; else diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 356d7e897..d52b454ea 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -39,7 +39,8 @@ module unpack ( output logic XSubnorm, // is X subnormal output logic XZero, YZero, ZZero, // is XYZ zero output logic XInf, YInf, ZInf, // is XYZ infinity - output logic XExpMax // does X have the maximum exponent (NaN or Inf) + output logic XExpMax, // does X have the maximum exponent (NaN or Inf) + output logic [`FLEN-1:0] XPostBox // X after being properly NaN-boxed ); logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero @@ -48,14 +49,17 @@ module unpack ( unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero), - .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm)); + .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), + .Subnorm(XSubnorm), .PostBox(XPostBox)); unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero), - .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm()); + .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), + .Subnorm(), .PostBox()); unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero), - .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm()); + .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), + .Subnorm(), .PostBox()); endmodule \ No newline at end of file diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index 68f98e900..36e3448ca 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -40,13 +40,14 @@ module unpackinput ( output logic Inf, // is the number infinity output logic ExpNonZero, // is the exponent not zero output logic FracZero, // is the fraction zero - output logic ExpMax, // does In have the maximum exponent (NaN or Inf) - output logic Subnorm // is the number subnormal + output logic ExpMax, // does In have the maximum exponent (NaN or Inf) + output logic Subnorm, // is the number subnormal + output logic [`FLEN-1:0] PostBox // Number reboxed correctly as a NaN ); logic [`NF-1:0] Frac; // Fraction of XYZ - logic BadNaNBox; // is the NaN boxing bad - + logic BadNaNBox; // incorrectly NaN Boxed + if (`FPSIZES == 1) begin // if there is only one floating point format supported assign BadNaNBox = 0; assign Sgn = In[`FLEN-1]; // sign bit @@ -54,6 +55,7 @@ module unpackinput ( assign ExpNonZero = |In[`FLEN-2:`NF]; // is the exponent non-zero assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero}; // exponent. subnormal numbers have effective biased exponent of 1 assign ExpMax = &In[`FLEN-2:`NF]; // is the exponent all 1's + assign PostBox = In; end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported // largest format | smaller format @@ -75,6 +77,11 @@ module unpackinput ( // double and half assign BadNaNBox = ~(Fmt|(&In[`FLEN-1:`LEN1])); // Check NaN boxing + always_comb + if (BadNaNBox) begin + PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]}; + end else + PostBox = In; // choose sign bit depending on format - 1=larger precsion 0=smaller precision assign Sgn = Fmt ? In[`FLEN-1] : In[`LEN1-1]; @@ -128,6 +135,17 @@ module unpackinput ( default: BadNaNBox = 1'bx; endcase + always_comb + if (BadNaNBox) begin + case (Fmt) + `FMT: PostBox = In; + `FMT1: PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]}; + `FMT2: PostBox = {{(`FLEN-`LEN2){1'b1}}, 1'b1, {(`NE2+1){1'b1}}, In[`LEN2-`NE2-3:0]}; + default: PostBox = 'x; + endcase + end else + PostBox = In; + // extract the sign bit always_comb case (Fmt) @@ -200,6 +218,17 @@ module unpackinput ( 2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN]; endcase + always_comb + if (BadNaNBox) begin + case (Fmt) + 2'b11: PostBox = In; + 2'b01: PostBox = {{(`Q_LEN-`D_LEN){1'b1}}, 1'b1, {(`D_NE+1){1'b1}}, In[`D_LEN-`D_NE-3:0]}; + 2'b00: PostBox = {{(`Q_LEN-`S_LEN){1'b1}}, 1'b1, {(`S_NE+1){1'b1}}, In[`S_LEN-`S_NE-3:0]}; + 2'b10: PostBox = {{(`Q_LEN-`H_LEN){1'b1}}, 1'b1, {(`H_NE+1){1'b1}}, In[`H_LEN-`H_NE-3:0]}; + endcase + end else + PostBox = In; + // extract sign bit always_comb case (Fmt) From 7923d32c3aa0be01118cf16ca4f6269933237630 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 18 Feb 2023 05:25:38 -0800 Subject: [PATCH 27/30] Fixed unpacking of illegal NaN box. Fixed issue #56 of sign injection NaN --- src/fpu/unpackinput.sv | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index 36e3448ca..c2b7e545d 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -79,7 +79,8 @@ module unpackinput ( assign BadNaNBox = ~(Fmt|(&In[`FLEN-1:`LEN1])); // Check NaN boxing always_comb if (BadNaNBox) begin - PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]}; +// PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]}; + PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, {(`LEN1-`NE1-2){1'b0}}}; end else PostBox = In; @@ -139,8 +140,10 @@ module unpackinput ( if (BadNaNBox) begin case (Fmt) `FMT: PostBox = In; - `FMT1: PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]}; - `FMT2: PostBox = {{(`FLEN-`LEN2){1'b1}}, 1'b1, {(`NE2+1){1'b1}}, In[`LEN2-`NE2-3:0]}; +// `FMT1: PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, In[`LEN1-`NE1-3:0]}; +// `FMT2: PostBox = {{(`FLEN-`LEN2){1'b1}}, 1'b1, {(`NE2+1){1'b1}}, In[`LEN2-`NE2-3:0]}; + `FMT1: PostBox = {{(`FLEN-`LEN1){1'b1}}, 1'b1, {(`NE1+1){1'b1}}, {(`LEN1-`NE1-2){1'b0}}}; + `FMT2: PostBox = {{(`FLEN-`LEN2){1'b1}}, 1'b1, {(`NE2+1){1'b1}}, {(`LEN2-`NE2-2){1'b0}}}; default: PostBox = 'x; endcase end else @@ -222,9 +225,12 @@ module unpackinput ( if (BadNaNBox) begin case (Fmt) 2'b11: PostBox = In; - 2'b01: PostBox = {{(`Q_LEN-`D_LEN){1'b1}}, 1'b1, {(`D_NE+1){1'b1}}, In[`D_LEN-`D_NE-3:0]}; - 2'b00: PostBox = {{(`Q_LEN-`S_LEN){1'b1}}, 1'b1, {(`S_NE+1){1'b1}}, In[`S_LEN-`S_NE-3:0]}; - 2'b10: PostBox = {{(`Q_LEN-`H_LEN){1'b1}}, 1'b1, {(`H_NE+1){1'b1}}, In[`H_LEN-`H_NE-3:0]}; +// 2'b01: PostBox = {{(`Q_LEN-`D_LEN){1'b1}}, 1'b1, {(`D_NE+1){1'b1}}, In[`D_LEN-`D_NE-3:0]}; +// 2'b00: PostBox = {{(`Q_LEN-`S_LEN){1'b1}}, 1'b1, {(`S_NE+1){1'b1}}, In[`S_LEN-`S_NE-3:0]}; +// 2'b10: PostBox = {{(`Q_LEN-`H_LEN){1'b1}}, 1'b1, {(`H_NE+1){1'b1}}, In[`H_LEN-`H_NE-3:0]}; + 2'b01: PostBox = {{(`Q_LEN-`D_LEN){1'b1}}, 1'b1, {(`D_NE+1){1'b1}}, {(`D_LEN-`D_NE-2){1'b0}}}; + 2'b00: PostBox = {{(`Q_LEN-`S_LEN){1'b1}}, 1'b1, {(`S_NE+1){1'b1}}, {(`S_LEN-`S_NE-2){1'b0}}}; + 2'b10: PostBox = {{(`Q_LEN-`H_LEN){1'b1}}, 1'b1, {(`H_NE+1){1'b1}}, {(`H_LEN-`H_NE-2){1'b0}}}; endcase end else PostBox = In; From adc22235bef77e3667de3584b009f96d9173396c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 18 Feb 2023 05:34:40 -0800 Subject: [PATCH 28/30] Fixed issue #57 of sign selection for improperly NaN-boxed number --- src/fpu/unpackinput.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index c2b7e545d..82a2eb8f1 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -85,7 +85,7 @@ module unpackinput ( PostBox = In; // choose sign bit depending on format - 1=larger precsion 0=smaller precision - assign Sgn = Fmt ? In[`FLEN-1] : In[`LEN1-1]; + assign Sgn = Fmt ? In[`FLEN-1] : (BadNaNBox ? 0 : In[`LEN1-1]); // improperly boxed NaNs are treated as positive // extract the fraction, add trailing zeroes to the mantissa if nessisary assign Frac = Fmt ? In[`NF-1:0] : {In[`NF1-1:0], (`NF-`NF1)'(0)}; @@ -151,6 +151,8 @@ module unpackinput ( // extract the sign bit always_comb + if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive + else case (Fmt) `FMT: Sgn = In[`FLEN-1]; `FMT1: Sgn = In[`LEN1-1]; @@ -158,7 +160,7 @@ module unpackinput ( default: Sgn = 1'bx; endcase - // extract the fraction + // extract the fraction always_comb case (Fmt) `FMT: Frac = In[`NF-1:0]; @@ -237,6 +239,8 @@ module unpackinput ( // extract sign bit always_comb + if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive + else case (Fmt) 2'b11: Sgn = In[`Q_LEN-1]; 2'b01: Sgn = In[`D_LEN-1]; From 1af99c7aee03b122c100eaad5da3a6a445c18ad4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 18 Feb 2023 05:57:39 -0800 Subject: [PATCH 29/30] Removed unused weq0M register fron fdivsqrtpostproc --- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 44b269355..b09e9f385 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -49,7 +49,7 @@ module fdivsqrtpostproc( logic [`DIVb+3:0] W, Sum, DM; logic [`DIVb:0] PreQmM; logic NegStickyM; - logic weq0E, weq0M, WZeroM; + logic weq0E, WZeroM; logic [`XLEN-1:0] IntDivResultM; ////////////////////////// @@ -81,7 +81,6 @@ module fdivsqrtpostproc( ////////////////////////// flopenr #(1) WZeroMReg(clk, reset, ~StallM, WZeroE, WZeroM); - flopenr #(1) WeqZeroMReg(clk, reset, ~StallM, weq0E, weq0M); ////////////////////////// // Memory Stage: Postprocessing From 92d4acf118e29481e248efabad2a903e95613e73 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 18 Feb 2023 05:59:25 -0800 Subject: [PATCH 30/30] Removed unused PredInstrClassE register from bpred --- src/ifu/bpred/bpred.sv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index f50232527..a65633c92 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -72,7 +72,7 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; @@ -207,8 +207,7 @@ module bpred ( // pipeline the class flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE); - flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE); - + // Check the prediction // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address. // if the class prediction is wrong a regular instruction may have been predicted as a taken branch