From 9bf0eedf73b5c36c7847456509fbb4a458bd11bf Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 4 Dec 2022 12:30:56 -0600
Subject: [PATCH] Optimized way selection logic.

---
 pipelined/src/cache/cache.sv    |  2 +-
 pipelined/src/cache/cacheLRU.sv |  6 +++---
 pipelined/src/cache/cacheway.sv | 13 +++++--------
 3 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index aff5ac70d..d00690dc8 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -132,7 +132,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   if(NUMWAYS > 1) begin:vict
     cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
       .clk, .reset, .ce, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage),
-      .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
+      .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
   end else assign VictimWay = 1'b1; // one hot.
   assign CacheHit = | HitWay;
   assign VictimDirty = | VictimDirtyWay;
diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv
index 9a7038f4c..f6d5adf57 100644
--- a/pipelined/src/cache/cacheLRU.sv
+++ b/pipelined/src/cache/cacheLRU.sv
@@ -38,7 +38,7 @@ module cacheLRU
    output logic [NUMWAYS-1:0] VictimWay,
    input logic [SETLEN-1:0]   CAdr,
    input logic [SETLEN-1:0]   PAdr,
-   input logic                LRUWriteEn, SetValid, InvalidateCache);
+   input logic                LRUWriteEn, SetValid, InvalidateCache, FlushCache);
 
   logic [NUMWAYS-2:0]                  LRUMemory [NUMLINES-1:0];
   logic [NUMWAYS-2:0]                  CurrLRU;
@@ -121,9 +121,9 @@ module cacheLRU
   always_ff @(posedge clk) begin
     if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
     if(ce) begin
-      if(InvalidateCache & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
+      if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
       else if (LRUWriteEn & ~FlushStage) begin 
-        LRUMemory[PAdr] <= NextLRU;
+        LRUMemory[CAdr] <= NextLRU; ///***** RT: This is not right. Logically should be PAdr, but it breaks linux.
         CurrLRU <= #1 NextLRU;
       end else begin
         CurrLRU <= #1 LRUMemory[CAdr];
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index 6865bf110..b8f809942 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -68,7 +68,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic [LINELEN-1:0]                ReadDataLine;
   logic [TAGLEN-1:0]                 ReadTag;
   logic                              Dirty;
-  logic                              SelData;
   logic                              SelTag;
   logic                              SelectedWriteWordEn;
   logic [LINELEN/8-1:0]              FinalByteMask;
@@ -79,14 +78,15 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic                              ClearDirtyWay;
   logic                              SelectedWay;
   
+  mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
+  mux2 #(1) selectedwaymux(HitWay, SelTag, SelFlush | SetValid | SelEvict, SelectedWay);
+
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Enable demux
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  mux2 #(1) selectedwaymux(HitWay, SelTag, SelFlush | SetValid, SelectedWay);
-
   // RT: Can we merge these two muxes?  This is also shared in cacheLRU.
-  //  mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay,     {SelFlush, SetValid}, SelectedWay);
+  //mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay,     {SelFlush, SetValid}, SelectedWay);
   //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
 
   assign SetValidWay = SetValid & SelectedWay;
@@ -110,7 +110,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   
 
   // AND portion of distributed tag multiplexer
-  mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
   assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux
   assign VictimDirtyWay = SelTag & Dirty & ValidWay;
   assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
@@ -134,9 +133,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   end
 
   // AND portion of distributed read multiplexers
-  //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData);
-  mux2 #(1) selecteddatamux(HitWay, SelTag, SelFlush | SelEvict, SelData);
-  assign ReadDataLineWay = SelData ? ReadDataLine : '0;  // AND part of AO mux.
+  assign ReadDataLineWay = SelectedWay ? ReadDataLine : '0;  // AND part of AO mux.
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Valid Bits