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neat verilog thing

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This commit is contained in:
Noah Boorstin 2021-04-18 17:48:51 -04:00
parent 0fa32ae5d6
commit 9bb1233433
2 changed files with 7 additions and 2 deletions
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6
wally-pipelined/src/ebu/ahblite.sv
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@ -30,6 +30,10 @@
`include "wally-config.vh" `include "wally-config.vh"
package ahbliteState;
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype;
endpackage
module ahblite ( module ahblite (
input logic clk, reset, input logic clk, reset,
input logic StallW, FlushW, input logic StallW, FlushW,
@ -90,7 +94,7 @@ module ahblite (
// Data accesses have priority over instructions. However, if a data access comes // Data accesses have priority over instructions. However, if a data access comes
// while an instruction read is occuring, the instruction read finishes before // while an instruction read is occuring, the instruction read finishes before
// the data access can take place. // the data access can take place.
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype; import ahbliteState::*;
statetype BusState, NextBusState; statetype BusState, NextBusState;
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);

3
wally-pipelined/testbench/testbench-busybear.sv
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@ -191,9 +191,10 @@ module testbench_busybear();
logic [`XLEN-1:0] readAdrExpected; logic [`XLEN-1:0] readAdrExpected;
import ahbliteState::*;
always @(dut.HRDATA) begin always @(dut.HRDATA) begin
#2; #2;
if (dut.hart.MemRWM[1] && ~HWRITE && HADDR[31:3] != dut.PCF[31:3] && dut.HRDATA !== {64{1'bx}}) begin if (dut.hart.MemRWM[1] && ~HWRITE && dut.hart.ebu.BusState == MEMREAD && dut.HRDATA !== {64{1'bx}}) begin
//$display("%0t", $time); //$display("%0t", $time);
if($feof(data_file_memR)) begin if($feof(data_file_memR)) begin
$display("no more memR data to read"); $display("no more memR data to read");