From 9ba35991e36517ff1ccb0818bce59ccd8ae3f9a0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Feb 2024 20:01:28 -0800 Subject: [PATCH] Finished FPU coverage --- sim/coverage-exclusions-rv64gc.do | 2 ++ src/fpu/postproc/cvtshiftcalc.sv | 2 +- testbench/tests.vh | 11 +++++++++-- tests/coverage/fpu.S | 22 ---------------------- 4 files changed, 12 insertions(+), 25 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 3c0e0dd48..36098d90d 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -49,6 +49,8 @@ coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLi # Division by zero never sets sticky/guard/overflow/round to cause inexact or underflow result, but check out of paranoia coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15 coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22 +# Convert int to fp will never underflow +coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ../src/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4 ################## # Cache Exclusions diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 8a35fa68f..8b7587e49 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -99,6 +99,6 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( // determine if the result underflows ??? -> fp // - if the first 1 is shifted out of the result then the result underflows // - can't underflow an integer to fp conversions - assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero; // dh 2/15/24 removed &~IntToFp, which is never limiting because int to fp will not underflow + assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; endmodule diff --git a/testbench/tests.vh b/testbench/tests.vh index 11afd2224..95ebb74b3 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -45,8 +45,6 @@ string tvpaths[] = '{ string coverage64gc[] = '{ `COVERAGE, - "tlbmisc", - "tlbNAPOT", "ieu", "priv", "ebu", @@ -55,6 +53,8 @@ string tvpaths[] = '{ "fpu", "lsu", "vm64check", + "tlbmisc", + "tlbNAPOT", "tlbASID", "tlbGLB", "tlbMP", @@ -2156,6 +2156,13 @@ string arch64zbs[] = '{ string arch64zfad[] = '{ `RISCVARCHTEST, + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S", "rv64i_m/D_Zfa/src/fleq_b1-01.S", "rv64i_m/D_Zfa/src/fleq_b19-01.S", "rv64i_m/D_Zfa/src/fli.d-01.S", diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index a88ed8a51..497ba0207 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -198,28 +198,6 @@ main: fcvt.s.w ft2, zero fdiv.s ft3, ft1, ft2 -/* These didn't make a difference - - // Test subtraction of identical denormalized numbers with to exercise FmaPreResultSubnorm logic with FmaSZero - li t0, 0xFFFFFFFF00000001 - fmv.w.x ft1, t0 // smallest denorm - fsub.s ft1, ft1, ft1 // difference = 0 - - li t0, 0x0000000000000001 - fmv.d.x ft1, t0 // smallest denorm - fsub.d ft1, ft1, ft1 // difference = 0 - - // Test subtraction of identical denormalized numbers with to exercise FmaPreResultSubnorm logic with FmaSZero - li t0, 0xFFFFFFFF00100001 - fmv.w.x ft1, t0 // almost largest denorm - fsub.s ft1, ft1, ft1 // difference = 0 - - li t0, 0x0001000000000001 - fmv.d.x ft1, t0 // smallest denorm - fsub.d ft1, ft1, ft1 // difference = 0 - -*/ - # Test floating point convert to integer and using result fcvt.w.s t0, f0 add t1, t0, t0