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Improved critical path.

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This commit is contained in:
Ross Thompson 2023-07-19 14:59:37 -05:00
parent 936b2a8c8b
commit 9ba3113e9c
1 changed files with 4 additions and 2 deletions
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6
src/mmu/hptw.sv
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@ -142,7 +142,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
if(P.SVADU_SUPPORTED) begin : hptwwrites
logic ReadAccess, WriteAccess;
logic InvalidRead, InvalidWrite, InvalidOp;
logic UpperBitsUnequal;
logic UpperBitsUnequal, UpperBitsUnequalD;
logic OtherPageFault;
logic [1:0] EffectivePrivilegeMode;
logic ImproperPrivilege;
@ -172,10 +172,12 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// Check for page faults
vm64check #(P) vm64check(.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .VAdr(TranslationVAdr),
.SV39Mode(), .UpperBitsUnequal);
// This register is not functionally necessary, but improves the critical path.
flopr #(1) upperbitsunequalreg(clk, reset, UpperBitsUnequal, UpperBitsUnequalD);
assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
assign InvalidWrite = WriteAccess & ~Writable;
assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid;
assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequalD | Misaligned | ~Valid;
// hptw needs to know if there is a Dirty or Access fault occuring on this
// memory access. If there is the PTE needs to be updated seting Access