Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Cleanup comments.

Browse Source
This commit is contained in:
Ross Thompson 2022-12-16 17:08:35 -06:00
parent 5f556817c7
commit 9b9e954cc5
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/lsu/lsu.sv
View File

@ -31,7 +31,6 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
// committed means the memory operation in flight cannot be interrupted. // committed means the memory operation in flight cannot be interrupted.
// cpubusy means the cpu is stalled and the lsu must ensure ReadDataM stalls constant until the stall is removed.
// chap 5 handling faults to memory by delaying writes to memory stage. // chap 5 handling faults to memory by delaying writes to memory stage.
// chap 6 combing bus with dtim // chap 6 combing bus with dtim
// chap 9 complete lsu. // chap 9 complete lsu.
@ -285,7 +284,6 @@ module lsu (
logic [1:0] BusRW; logic [1:0] BusRW;
logic [`XLEN-1:0] FetchBuffer; logic [`XLEN-1:0] FetchBuffer;
assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
// assign BusRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{SelDTIM, SelDTIM};
assign LSUHADDR = PAdrM; assign LSUHADDR = PAdrM;
assign LSUHSIZE = LSUFunct3M; assign LSUHSIZE = LSUFunct3M;