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Merge pull request #524 from davidharrishmc/main

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Renamed HADE to ADUE for Svadu
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Rose Thompson 2023-12-13 11:53:38 -08:00 committed by GitHub
commit 9b7c47caa4
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14 changed files with 38 additions and 38 deletions
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2
sim/imperas.ic
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@ -54,7 +54,7 @@
--override cpu/misa_Extensions_mask=0x0 --override cpu/misa_Extensions_mask=0x0
--override cpu/Sstc=T --override cpu/Sstc=T
# Enable SVADU hardware update of A/D bits when menvcfg.HADE=1 # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
--override cpu/Svadu=T --override cpu/Svadu=T
--override cpu/updatePTEA=F --override cpu/updatePTEA=F
--override cpu/updatePTED=F --override cpu/updatePTED=F

4
src/ifu/ifu.sv
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@ -86,7 +86,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
input logic STATUS_MPRV, // Status CSR: modify machine privilege input logic STATUS_MPRV, // Status CSR: modify machine privilege
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_PBMTE, // Page-based memory types enabled
input logic ENVCFG_HADE, // HPTW A/D Update enable input logic ENVCFG_ADUE, // HPTW A/D Update enable
input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
@ -168,7 +168,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
assign TLBFlush = sfencevmaM & ~StallMQ; assign TLBFlush = sfencevmaM & ~StallMQ;
mmu #(.P(P), .TLB_ENTRIES(P.ITLB_ENTRIES), .IMMU(1)) mmu #(.P(P), .TLB_ENTRIES(P.ITLB_ENTRIES), .IMMU(1))
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .DisableTranslation(1'b0), .PrivilegeModeW, .DisableTranslation(1'b0),
.VAdr(PCFExt), .VAdr(PCFExt),
.Size(2'b10), .Size(2'b10),

6
src/lsu/lsu.sv
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@ -81,7 +81,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
input logic [1:0] STATUS_MPP, // Machine previous privilege mode input logic [1:0] STATUS_MPP, // Machine previous privilege mode
input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_PBMTE, // Page-based memory types enabled
input logic ENVCFG_HADE, // HPTW A/D Update enable input logic ENVCFG_ADUE, // HPTW A/D Update enable
input logic [P.XLEN-1:0] PCSpillF, // Fetch PC input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
@ -192,7 +192,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM, .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF, .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_HADE, .PrivilegeModeW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
.WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
@ -230,7 +230,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign DisableTranslation = SelHPTW | FlushDCacheM; assign DisableTranslation = SelHPTW | FlushDCacheM;
assign WriteAccessM = PreLSURWM[0]; assign WriteAccessM = PreLSURWM[0];
mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0)) mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]), .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM), .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),

12
src/mmu/hptw.sv
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@ -38,7 +38,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// system status // system status
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic ENVCFG_HADE, // HPTW A/D Update enable input logic ENVCFG_ADUE, // HPTW A/D Update enable
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [P.XLEN-1:0] ReadDataM, // page table entry from LSU input logic [P.XLEN-1:0] ReadDataM, // page table entry from LSU
input logic [P.XLEN-1:0] WriteDataM, input logic [P.XLEN-1:0] WriteDataM,
@ -154,7 +154,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] AccessedPTE; logic [P.XLEN-1:0] AccessedPTE;
assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when HADE = 0 because UpdatePTE = 0 mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0
flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
assign SaveHPTWAdr = WalkerState == L0_ADR; assign SaveHPTWAdr = WalkerState == L0_ADR;
@ -183,11 +183,11 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// hptw needs to know if there is a Dirty or Access fault occuring on this // hptw needs to know if there is a Dirty or Access fault occuring on this
// memory access. If there is the PTE needs to be updated seting Access // memory access. If there is the PTE needs to be updated seting Access
// and possibly also Dirty. Dirty is set if the operation is a store/amo. // and possibly also Dirty. Dirty is set if the operation is a store/amo.
// However any other fault should not cause the update, and updates are in software when ENVCFG_HADE = 0 // However any other fault should not cause the update, and updates are in software when ENVCFG_ADUE = 0
assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_HADE & ~OtherPageFault; assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault;
assign HPTWRW[0] = (WalkerState == UPDATE_PTE); // HPTWRW[0] will always be 0 if HADE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE assign HPTWRW[0] = (WalkerState == UPDATE_PTE); // HPTWRW[0] will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE
assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if HADE = 0 because HPTWUpdateDA will be 0 assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
end else begin // block: hptwwrites end else begin // block: hptwwrites
assign NextPTE = ReadDataM; assign NextPTE = ReadDataM;

4
src/mmu/mmu.sv
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@ -35,7 +35,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
input logic STATUS_MPRV, // Status CSR: modify machine privilege input logic STATUS_MPRV, // Status CSR: modify machine privilege
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_PBMTE, // Page-based memory types enabled
input logic ENVCFG_HADE, // HPTW A/D Update enable input logic ENVCFG_ADUE, // HPTW A/D Update enable
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
input logic [P.XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW input logic [P.XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW
@ -84,7 +84,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
.clk, .reset, .clk, .reset,
.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
.SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]), .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
.VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp,
.DisableTranslation, .PTE, .PageTypeWriteVal, .DisableTranslation, .PTE, .PageTypeWriteVal,
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,

4
src/mmu/tlb/tlb.sv
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@ -58,7 +58,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_PBMTE, // Page-based memory types enabled
input logic ENVCFG_HADE, // HPTW A/D Update enable input logic ENVCFG_ADUE, // HPTW A/D Update enable
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
input logic ReadAccess, input logic ReadAccess,
input logic WriteAccess, input logic WriteAccess,
@ -106,7 +106,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
assign VPN = VAdr[P.VPN_BITS+11:12]; assign VPN = VAdr[P.VPN_BITS+11:12];
tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush, .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush,
.PTEAccessBits, .CAMHit, .Misaligned, .PTEAccessBits, .CAMHit, .Misaligned,
.TLBMiss, .TLBHit, .TLBPageFault, .TLBMiss, .TLBHit, .TLBPageFault,

6
src/mmu/tlb/tlbcontrol.sv
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@ -32,7 +32,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_PBMTE, // Page-based memory types enabled
input logic ENVCFG_HADE, // HPTW A/D Update enable input logic ENVCFG_ADUE, // HPTW A/D Update enable
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
input logic ReadAccess, WriteAccess, input logic ReadAccess, WriteAccess,
input logic [3:0] CMOp, input logic [3:0] CMOp,
@ -119,10 +119,10 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
end end
// Determine wheter to update DA bits. With SVADU, it is done in hardware // Determine wheter to update DA bits. With SVADU, it is done in hardware
assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE; assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_ADUE;
// Determine whether page fault occurs // Determine whether page fault occurs
assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE)); assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_ADUE));
assign TLBPageFault = Translate & TLBHit & (PrePageFault | InvalidAccess); assign TLBPageFault = Translate & TLBHit & (PrePageFault | InvalidAccess);
assign TLBHit = CAMHit & TLBAccess; assign TLBHit = CAMHit & TLBAccess;

4
src/privileged/csr.sv
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@ -85,7 +85,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
output logic [2:0] FRM_REGW, output logic [2:0] FRM_REGW,
output logic [3:0] ENVCFG_CBE, output logic [3:0] ENVCFG_CBE,
output logic ENVCFG_PBMTE, // Page-based memory type enable output logic ENVCFG_PBMTE, // Page-based memory type enable
output logic ENVCFG_HADE, // HPTW A/D Update enable output logic ENVCFG_ADUE, // HPTW A/D Update enable
// //
output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR
output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
@ -292,7 +292,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
// Broadcast appropriate environment configuration based on privilege mode // Broadcast appropriate environment configuration based on privilege mode
assign ENVCFG_STCE = MENVCFG_REGW[63]; // supervisor timer counter enable assign ENVCFG_STCE = MENVCFG_REGW[63]; // supervisor timer counter enable
assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable
assign ENVCFG_HADE = MENVCFG_REGW[61]; // Hardware A/D Update enable assign ENVCFG_ADUE = MENVCFG_REGW[61]; // Hardware A/D Update enable
assign ENVCFG_CBE = (PrivilegeModeW == P.M_MODE) ? 4'b1111 : assign ENVCFG_CBE = (PrivilegeModeW == P.M_MODE) ? 4'b1111 :
(PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] :
(MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]); (MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]);

4
src/privileged/privileged.sv
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@ -84,7 +84,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
output logic [2:0] FRM_REGW, // FPU rounding mode output logic [2:0] FRM_REGW, // FPU rounding mode
output logic [3:0] ENVCFG_CBE, // Cache block operation enables output logic [3:0] ENVCFG_CBE, // Cache block operation enables
output logic ENVCFG_PBMTE, // Page-based memory type enable output logic ENVCFG_PBMTE, // Page-based memory type enable
output logic ENVCFG_HADE, // HPTW A/D Update enable output logic ENVCFG_ADUE, // HPTW A/D Update enable
// PC logic output in privileged unit // PC logic output in privileged unit
output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
// control outputs // control outputs
@ -141,7 +141,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
.MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
.SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM); .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
// pipeline early-arriving trap sources // pipeline early-arriving trap sources

8
src/wally/wallypipelinedcore.sv
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@ -78,7 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
logic SquashSCW; logic SquashSCW;
logic MDUActiveE; // Mul/Div instruction being executed logic MDUActiveE; // Mul/Div instruction being executed
logic ENVCFG_HADE; // HPTW A/D Update enable logic ENVCFG_ADUE; // HPTW A/D Update enable
logic ENVCFG_PBMTE; // Page-based memory type enable logic ENVCFG_PBMTE; // Page-based memory type enable
logic [3:0] ENVCFG_CBE; // Cache Block operation enables logic [3:0] ENVCFG_CBE; // Cache Block operation enables
logic [3:0] CMOpM; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero logic [3:0] CMOpM; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
@ -185,7 +185,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM, .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
// mmu management // mmu management
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
.STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, .ITLBWriteF, .sfencevmaM, .ITLBMissF, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
// pmp/pma (inside mmu) signals. // pmp/pma (inside mmu) signals.
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF); .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF);
@ -234,7 +234,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.STATUS_MPRV, // from csr .STATUS_MPRV, // from csr
.STATUS_MPP, // from csr .STATUS_MPP, // from csr
.ENVCFG_PBMTE, // from csr .ENVCFG_PBMTE, // from csr
.ENVCFG_HADE, // from csr .ENVCFG_ADUE, // from csr
.sfencevmaM, // connects to privilege .sfencevmaM, // connects to privilege
.DCacheStallM, // connects to privilege .DCacheStallM, // connects to privilege
.LoadPageFaultM, // connects to privilege .LoadPageFaultM, // connects to privilege
@ -296,7 +296,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.PrivilegeModeW, .SATP_REGW, .PrivilegeModeW, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .wfiM, .IntPendingM, .BigEndianM); .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
end else begin end else begin
assign CSRReadValW = 0; assign CSRReadValW = 0;
assign UnalignedPCNextF = PC2NextF; assign UnalignedPCNextF = PC2NextF;

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
View File

@ -42,8 +42,8 @@ beef0110
deadbeef # Test 11.3.1.3.7(a) successful read when D = 0 deadbeef # Test 11.3.1.3.7(a) successful read when D = 0
00000009 # call from going to m mode from s mode 00000009 # call from going to m mode from s mode
0000000b # ecall from going to S mode from m mode 0000000b # ecall from going to S mode from m mode
beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.HADE=1 beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.ADUE=1
beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and MENVCFG.HADE=1 beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and MENVCFG.ADUE=1
beef0077 # Test 11.3.1.4.1: successful read back of saved value with new memory mapping beef0077 # Test 11.3.1.4.1: successful read back of saved value with new memory mapping
00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode 00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
00000000 # previous value of mprv before being set 00000000 # previous value of mprv before being set

6
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
View File

@ -157,7 +157,7 @@ test_cases:
.4byte 0xBFFDE0, 0xbad, executable_test # instr page fault when X=0 .4byte 0xBFFDE0, 0xbad, executable_test # instr page fault when X=0
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits # In the following two tests, SVADU is supported, so the hardware handles the A/D bits
# Initially test with HADE = 0, so needing to set A/D bits triggers page fault # Initially test with ADUE = 0, so needing to set A/D bits triggers page fault
# test 11.3.1.3.6(a) Accessed flag == 0 # test 11.3.1.3.6(a) Accessed flag == 0
.4byte 0x3020, 0xBEEF0770, write32_test # store page fault when A=0 .4byte 0x3020, 0xBEEF0770, write32_test # store page fault when A=0
@ -167,9 +167,9 @@ test_cases:
.4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0 .4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0
.4byte 0x4658, 0xDEADBEEF, read32_test # read success when D=0; default DEADBEEF value wasn't changed .4byte 0x4658, 0xDEADBEEF, read32_test # read success when D=0; default DEADBEEF value wasn't changed
# Now set HADE bit # Now set ADUE bit
.4byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output .4byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
.4byte 0x0, 0x20000000, write_menvcfgh # set menvcfg.HADE = 1 .4byte 0x0, 0x20000000, write_menvcfgh # set menvcfg.ADUE = 1
.4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output .4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
# Since SVADU is 1, there are no faults when A/D=0 # Since SVADU is 1, there are no faults when A/D=0

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
View File

@ -196,7 +196,7 @@ test_cases:
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits # In the following two tests, SVADU is supported, so the hardware handles the A/D bits
# Initially test with HADE = 0, so needing to set A/D bits triggers page fault # Initially test with ADUE = 0, so needing to set A/D bits triggers page fault
# test 11.3.1.3.6(a) Accessed flag == 0 # test 11.3.1.3.6(a) Accessed flag == 0
.8byte 0x36D0, 0x0990DEADBEEF0770, write64_test# store page fault when A=0 .8byte 0x36D0, 0x0990DEADBEEF0770, write64_test# store page fault when A=0
@ -206,9 +206,9 @@ test_cases:
.8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0 .8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0
.8byte 0x4AA0, 0xDEADBEEFDEADBEEF, read64_test# read success when D=0 .8byte 0x4AA0, 0xDEADBEEFDEADBEEF, read64_test# read success when D=0
# Now set HADE bit # Now set ADUE bit
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1 .8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.ADUE = 1
.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
# Since SVADU is 1, there are no faults when A/D=0 # Since SVADU is 1, there are no faults when A/D=0

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
View File

@ -189,7 +189,7 @@ test_cases:
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits # In the following two tests, SVADU is supported, so the hardware handles the A/D bits
# Initially test with HADE = 0, so needing to set A/D bits triggers page fault # Initially test with ADUE = 0, so needing to set A/D bits triggers page fault
# test 11.3.1.3.6(a) Accessed flag == 0 # test 11.3.1.3.6(a) Accessed flag == 0
.8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # store page fault when A=0 .8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # store page fault when A=0
@ -199,9 +199,9 @@ test_cases:
.8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # store page fault when D=0 .8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # store page fault when D=0
.8byte 0x80204658, 0xDEADBEEFDEADBEEF, read64_test # read success when D=0 .8byte 0x80204658, 0xDEADBEEFDEADBEEF, read64_test # read success when D=0
# Now set HADE bit # Now set ADUE bit
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1 .8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.ADUE = 1
.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
# Since SVADU is 1, there are no faults when A/D=0 # Since SVADU is 1, there are no faults when A/D=0