From 9b4f3219dbe11d5acf5bca5f019ef7cfa25d9744 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:32:01 -0800 Subject: [PATCH] formatting --- src/ieu/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 6398e4fcf..c770a630b 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,12 +43,12 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned