From a5f773220e9cc7b71b8d11ecf71a541dda0c8602 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 18 Jan 2022 17:19:33 -0600 Subject: [PATCH] Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes. --- pipelined/src/privileged/csr.sv | 10 +++++----- pipelined/src/privileged/csri.sv | 13 ++++++++----- pipelined/src/privileged/csrm.sv | 31 +++++++++++++++++-------------- pipelined/src/privileged/csrn.sv | 15 +++++++++------ pipelined/src/privileged/csrs.sv | 21 ++++++++++++--------- pipelined/src/privileged/csru.sv | 11 +++++++---- 6 files changed, 58 insertions(+), 43 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 76dd0f272..d4110666b 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -119,7 +119,7 @@ module csr #(parameter assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRUWriteM = CSRWriteM; - csri csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM, + csri csri(.clk, .reset, .FlushW, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM); csrsr csrsr(.clk, .reset, .StallW, @@ -137,7 +137,7 @@ module csr #(parameter .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); - csrm csrm(.clk, .reset, .StallW, + csrm csrm(.clk, .reset, .FlushW, .StallW, .CSRMWriteM, .MTrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW, @@ -145,7 +145,7 @@ module csr #(parameter .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM); - csrs csrs(.clk, .reset, .StallW, + csrs csrs(.clk, .reset, .FlushW, .StallW, .CSRSWriteM, .STrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, @@ -153,12 +153,12 @@ module csr #(parameter .SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW, .SATP_REGW, .SIP_REGW, .SIE_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); - csrn csrn(.clk, .reset, .StallW, + csrn csrn(.clk, .reset, .FlushW, .StallW, .CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW, .CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW, .UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM); - csru csru(.clk, .reset, .StallW, + csru csru(.clk, .reset, .FlushW, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM, .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, .IllegalCSRUAccessM); diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 02783a517..7247de025 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -38,7 +38,7 @@ module csri #(parameter SIE = 12'h104, SIP = 12'h144) ( input logic clk, reset, - input logic StallW, + input logic FlushW, StallW, input logic CSRMWriteM, CSRSWriteM, input logic [11:0] CSRAdrM, input logic ExtIntM, TimerIntM, SwIntM, @@ -52,6 +52,9 @@ module csri #(parameter logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; + logic InstrValidNotFlushedM; + assign InstrValidNotFlushedM = ~StallW & ~FlushW; + // Determine which interrupts need to be set // assumes no N-mode user interrupts @@ -66,10 +69,10 @@ module csri #(parameter end // Interrupt Write Enables - assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & ~StallW; - assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & ~StallW; - assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & ~StallW; - assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & ~StallW; + assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM; + assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM; + assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM; + assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM; // Interrupt Pending and Enable Registers // MEIP, MTIP, MSIP are read-only diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index f73ae7a04..48f462df8 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -70,7 +70,7 @@ module csrm #(parameter MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222} ) ( input logic clk, reset, - input logic StallW, + input logic FlushW, StallW, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, @@ -95,6 +95,9 @@ module csrm #(parameter logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; + logic InstrValidNotFlushedM; + assign InstrValidNotFlushedM = ~StallW & ~FlushW; + // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop genvar i; if (`PMP_ENTRIES > 0) begin:pmp @@ -110,13 +113,13 @@ module csrm #(parameter else assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01); - assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~StallW & ~ADDRLocked[i]; + assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i]; flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]); if (`XLEN==64) begin - assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~StallW & ~CFGLocked[i]; + assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i]; flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]); end else begin - assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~StallW & ~CFGLocked[i]; + assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & InstrValidNotFlushedM & ~CFGLocked[i]; flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]); end end @@ -131,16 +134,16 @@ module csrm #(parameter assign MHARTID_REGW = 0; // Write machine Mode CSRs - assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & ~StallW; - assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & ~StallW; - assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & ~StallW; - assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & ~StallW; - assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & ~StallW; - assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & ~StallW; - assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & ~StallW; - assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & ~StallW; - assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & ~StallW; - assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & ~StallW; + assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM; + assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM; + assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM; + assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM; + assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & InstrValidNotFlushedM; + assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & InstrValidNotFlushedM; + assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & InstrValidNotFlushedM; + assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & InstrValidNotFlushedM; + assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & InstrValidNotFlushedM; + assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & InstrValidNotFlushedM; assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); diff --git a/pipelined/src/privileged/csrn.sv b/pipelined/src/privileged/csrn.sv index a3df916b7..458f15333 100644 --- a/pipelined/src/privileged/csrn.sv +++ b/pipelined/src/privileged/csrn.sv @@ -42,7 +42,7 @@ module csrn #(parameter UTVAL = 12'h043, UIP = 12'h044) ( input logic clk, reset, - input logic StallW, + input logic FlushW, StallW, input logic CSRNWriteM, UTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, @@ -61,12 +61,15 @@ module csrn #(parameter logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW; logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; + logic InstrValidNotFlushedM; + assign InstrValidNotFlushedM = ~StallW & ~FlushW; + // Write enables - assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & ~StallW; - assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & ~StallW; - assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & ~StallW; - assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & ~StallW; - assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & ~StallW; + assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & InstrValidNotFlushedM; + assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & InstrValidNotFlushedM; + assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & InstrValidNotFlushedM; + assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & InstrValidNotFlushedM; + assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & InstrValidNotFlushedM; // CSRs flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW); diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index 85b93384c..d0e20ec4d 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -52,7 +52,7 @@ module csrs #(parameter ) ( input logic clk, reset, - input logic StallW, + input logic FlushW, StallW, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, @@ -81,14 +81,17 @@ module csrs #(parameter logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; - assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & ~StallW; - assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & ~StallW; - assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & ~StallW; - assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & ~StallW; - assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & ~StallW; - assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & ~StallW; - assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & ~StallW; - assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & ~StallW; + logic InstrValidNotFlushedM; + assign InstrValidNotFlushedM = ~StallW & ~FlushW; + + assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; + assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; + assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; + assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM; + assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM; + assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM; + assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM; + assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM; // CSRs flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0 diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 9c8b586e8..088abe85f 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -37,7 +37,7 @@ module csru #(parameter FRM = 12'h002, FCSR = 12'h003) ( input logic clk, reset, - input logic StallW, + input logic FlushW, StallW, input logic CSRUWriteM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] CSRWriteValM, @@ -54,10 +54,13 @@ module csru #(parameter logic [2:0] NextFRMM; logic [4:0] NextFFLAGSM; + logic InstrValidNotFlushedM; + assign InstrValidNotFlushedM = ~StallW & ~FlushW; + // Write enables - //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & ~StallW; - assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & ~StallW; - assign WriteFFLAGSM = (CSRUWriteM & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & ~StallW; + //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; + assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM; + assign WriteFFLAGSM = (CSRUWriteM & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM; // Write Values assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];