From 9ac905b5c094f0040611c006e3cbc0ddfe332fcc Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 14 Jan 2023 16:49:44 -0800 Subject: [PATCH] sdc cleanup --- pipelined/src/uncore/sdc/SDC.sv | 2 - pipelined/src/uncore/sdc/SDCcounter.sv | 4 +- pipelined/src/uncore/sdc/clkdivider.sv | 2 - pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 2 - pipelined/src/uncore/sdc/crc7_pipo.sv | 2 - pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 2 - pipelined/src/uncore/sdc/piso_generic_ce.sv | 2 - .../src/uncore/sdc/regfile_p2r1w1_nibo.sv | 2 - .../src/uncore/sdc/regfile_p2r1w1bwen.sv | 17 ++--- pipelined/src/uncore/sdc/sd_clk_fsm.sv | 2 - pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 2 - pipelined/src/uncore/sdc/sd_dat_fsm.sv | 2 - pipelined/src/uncore/sdc/sd_top.sv | 4 +- pipelined/src/uncore/sdc/sd_top_wrapper.v | 69 ++++++++++++------- pipelined/src/uncore/sdc/simple_timer.sv | 2 - pipelined/src/uncore/sdc/sipo_generic_ce.sv | 3 - pipelined/src/uncore/sdc/up_down_counter.sv | 2 - 17 files changed, 52 insertions(+), 69 deletions(-) diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv index f8cb97743..5a10d6430 100644 --- a/pipelined/src/uncore/sdc/SDC.sv +++ b/pipelined/src/uncore/sdc/SDC.sv @@ -8,8 +8,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv index cac17b7cd..4c29b19d9 100644 --- a/pipelined/src/uncore/sdc/SDCcounter.sv +++ b/pipelined/src/uncore/sdc/SDCcounter.sv @@ -9,9 +9,7 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file // except in compliance with the License, or, at your option, the Apache License version 2.0. You diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv index a877b35f3..c62258efb 100644 --- a/pipelined/src/uncore/sdc/clkdivider.sv +++ b/pipelined/src/uncore/sdc/clkdivider.sv @@ -9,8 +9,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv index e229466b1..ae3ce2af9 100644 --- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv @@ -10,8 +10,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv index 213b2e029..9144495f4 100644 --- a/pipelined/src/uncore/sdc/crc7_pipo.sv +++ b/pipelined/src/uncore/sdc/crc7_pipo.sv @@ -11,8 +11,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv index 4eddfa7e8..4ada97afa 100644 --- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv @@ -9,8 +9,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv index fb7f70949..697dfa864 100644 --- a/pipelined/src/uncore/sdc/piso_generic_ce.sv +++ b/pipelined/src/uncore/sdc/piso_generic_ce.sv @@ -7,8 +7,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv index 52e78426b..9ee46b4b6 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv @@ -7,8 +7,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv index bfa7c7148..cff149e60 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv @@ -7,8 +7,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file @@ -36,18 +34,11 @@ module regfile_p2r1w1bwen #(parameter integer DEPTH = 10, parameter integer WIDT ); logic [WIDTH-1:0] regs [2**DEPTH-1:0]; - integer i; + integer i; - always_ff @(posedge clk) begin - if(we1) begin - for (i=0; i < WIDTH; i++) begin - if(we1bit[i]) begin - regs[wa1][i] <= wd1[i]; - end - end - end - end + always_ff @(posedge clk) + if (we1) // global write enable + regs[wa1] = wd1 & we1bit | regs[wa1] & ~we1bit; // bit write enable assign rd1 = regs[ra1]; - endmodule diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv index 949b0dc12..5c47e04f7 100644 --- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_clk_fsm.sv @@ -17,8 +17,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv index a5512031e..5c2296657 100644 --- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv @@ -8,8 +8,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv index 24c2c2bc2..c38073e34 100644 --- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_dat_fsm.sv @@ -10,8 +10,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv index 2344d2876..3cac14ed9 100644 --- a/pipelined/src/uncore/sdc/sd_top.sv +++ b/pipelined/src/uncore/sdc/sd_top.sv @@ -8,9 +8,7 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file // except in compliance with the License, or, at your option, the Apache License version 2.0. You diff --git a/pipelined/src/uncore/sdc/sd_top_wrapper.v b/pipelined/src/uncore/sdc/sd_top_wrapper.v index 32fedfaa8..96d1bbc46 100644 --- a/pipelined/src/uncore/sdc/sd_top_wrapper.v +++ b/pipelined/src/uncore/sdc/sd_top_wrapper.v @@ -1,38 +1,61 @@ +/////////////////////////////////////////// +// sd_top_wrapper.sv +// +// Written: Richard Davis +// Modified: Ross Thompson September 19, 2021 +// +// Purpose: SD card controller wrapper +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +/// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8) ( - input clk_in1_p, - input clk_in1_n, - input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles) + input logic clk_in1_p, + input logic clk_in1_n, + input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles) // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK! // io_SD_CMD_z : inout std_logic; // SD CMD Bus - inout SD_CMD, // CMD Response from card - input [3:0] i_SD_DAT, // SD DAT Bus - output o_SD_CLK, // SD CLK Bus + inout SD_CMD, // CMD Response from card + input logic [3:0] i_SD_DAT, // SD DAT Bus + output logic o_SD_CLK, // SD CLK Bus // For communication with core cpu - output o_READY_FOR_READ, // tells core that initialization sequence is completed and + output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and // sd card is ready to read a 512 byte block to the core. // Held high during idle until i_READ_REQUEST is received - output o_SD_RESTARTING, // inform core the need to restart + output logic o_SD_RESTARTING, // inform core the need to restart - input i_READ_REQUEST, // After Ready for read is sent to the core, the core will + input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will // pulse this bit high to indicate it wants the block at this address - output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is - // being published - output o_DATA_VALID // held high while data being read to core to indicate that it is valid + output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is being published + output logic o_DATA_VALID // held high while data being read to core to indicate that it is valid ); - wire CLK; - wire LIMIT_SD_TIMERS; - wire [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX; - wire [4095:0] ReadData; // full 512 bytes to Bus - wire [32:9] i_BLOCK_ADDR; // see "Addressing" in parts.fods (only 8GB total capacity is used) - wire o_SD_CMD; // CMD Command from host - wire i_SD_CMD; // CMD Command from host - wire o_SD_CMD_OE; // Direction of SD_CMD - wire [2:0] o_ERROR_CODE_Q; // indicates which error occured - wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated - wire o_LAST_NIBBLE; // pulse when last nibble is sent + wire CLK; + wire LIMIT_SD_TIMERS; + wire [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX; + wire [4095:0] ReadData; // full 512 bytes to Bus + wire [32:9] i_BLOCK_ADDR; // see "Addressing" in parts.fods (only 8GB total capacity is used) + wire o_SD_CMD; // CMD Command from host + wire i_SD_CMD; // CMD Command from host + wire o_SD_CMD_OE; // Direction of SD_CMD + wire [2:0] o_ERROR_CODE_Q; // indicates which error occured + wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated + wire o_LAST_NIBBLE; // pulse when last nibble is sent assign LIMIT_SD_TIMERS = 1'b0; assign i_COUNT_IN_MAX = -8'd62; diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv index 6c6014d3e..09dbf048c 100644 --- a/pipelined/src/uncore/sdc/simple_timer.sv +++ b/pipelined/src/uncore/sdc/simple_timer.sv @@ -8,8 +8,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv index 39d61d588..7b749b654 100644 --- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv +++ b/pipelined/src/uncore/sdc/sipo_generic_ce.sv @@ -7,12 +7,9 @@ // Purpose: serial to n-bit parallel shift register using register_ce. // When given a n-bit word as input transmit the message serially MSB (leftmost) // bit first. - // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv index db8502e46..4424386ac 100644 --- a/pipelined/src/uncore/sdc/up_down_counter.sv +++ b/pipelined/src/uncore/sdc/up_down_counter.sv @@ -8,8 +8,6 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file