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LSU cleanup

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This commit is contained in:
David Harris 2021-07-17 20:01:03 -04:00
parent d9750c16a5
commit 9a86fc899b
1 changed files with 0 additions and 3 deletions
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wally-pipelined/src/lsu/lsu.sv
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@ -180,7 +180,6 @@ module lsu
else assign TranslationPAdrXLEN = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; else assign TranslationPAdrXLEN = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
endgenerate endgenerate
mux2 #(`XLEN) HPTWPAdrMux(TranslationPAdrXLEN, TranslationVAdr, UseTranslationVAdr, HPTWPAdrE); // *** misleading to call it PAdr, bad because some bits have been truncated mux2 #(`XLEN) HPTWPAdrMux(TranslationPAdrXLEN, TranslationVAdr, UseTranslationVAdr, HPTWPAdrE); // *** misleading to call it PAdr, bad because some bits have been truncated
// flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
@ -191,7 +190,6 @@ module lsu
.SelPTW(SelPTW), .SelPTW(SelPTW),
.HPTWRead(HPTWRead), .HPTWRead(HPTWRead),
.HPTWPAdrE(HPTWPAdrE), .HPTWPAdrE(HPTWPAdrE),
// .HPTWPAdrM(HPTWPAdrM),
.HPTWStall(HPTWStall), .HPTWStall(HPTWStall),
// CPU connection // CPU connection
.MemRWM(MemRWM), .MemRWM(MemRWM),
@ -246,7 +244,6 @@ module lsu
.Cacheable(CacheableM), .Cacheable(CacheableM),
.Idempotent(), .Idempotent(),
.AtomicAllowed(), .AtomicAllowed(),
// .SelRegions(DHSELRegionsM),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
// *** BUG, this is most likely wrong // *** BUG, this is most likely wrong