diff --git a/.gitignore b/.gitignore
index 3d3d875f0..7e6809e84 100644
--- a/.gitignore
+++ b/.gitignore
@@ -123,7 +123,7 @@ sim/test1.rep
 sim/questa/vsim.log
 tests/coverage/*.elf
 *.elf.memfile
-sim/*Cache.log
+sim/*/*Cache.log
 sim/branch
 tests/fp/combined_IF_vectors/IF_vectors/*.tv
 /sim/branch-march14.tar.gz
diff --git a/bin/CacheSim.py b/bin/CacheSim.py
index f6b2cb7e1..447ed9145 100755
--- a/bin/CacheSim.py
+++ b/bin/CacheSim.py
@@ -41,7 +41,6 @@
 # Add -d or --dist to report the distribution of loads, stores, and atomic ops.
 # These distributions may not add up to 100; this is because of flushes or invalidations.
 
-import sys
 import math
 import argparse
 import os
diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py
index bc75fc13a..a33749803 100755
--- a/sim/rv64gc_CacheSim.py
+++ b/sim/rv64gc_CacheSim.py
@@ -7,7 +7,7 @@
 ## Created: 11 April 2023
 ## Modified: 12 April 2023
 ##
-## Purpose: Run the cache simulator on each rv64gc test suite in turn. 
+## Purpose: Run the cache simulator on each rv64gc test suite in turn.
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
 ## https://github.com/openhwgroup/cvw
@@ -16,24 +16,23 @@
 ##
 ## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 ##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You
 ## may obtain a copy of the License at
 ##
 ## https:##solderpad.org/licenses/SHL-2.1/
 ##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
+## Unless required by applicable law or agreed to in writing, any work distributed under the
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+## either express or implied. See the License for the specific language governing permissions
 ## and limitations under the License.
 ################################################################################################
-import sys
 import os
 import argparse
 
 # NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
 # This does not check the test output for correctness, run regression for that.
-# Add -p or --perf to report the hit/miss ratio. 
+# Add -p or --perf to report the hit/miss ratio.
 # Add -d or --dist to report the distribution of loads, stores, and atomic ops.
 # These distributions may not add up to 100; this is because of flushes or invalidations.
 
@@ -48,36 +47,38 @@ class bcolors:
     BOLD = '\033[1m'
     UNDERLINE = '\033[4m'
 
-# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
-tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",             
-             "arch64zi", "wally64a", "wally64periph", "wally64priv", 
-             "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
+# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m",
+tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",
+             "arch64zi", "wally64a", "wally64periph", "wally64priv",
+             "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs",
              "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
 # arch64i is the most interesting case.  Uncomment line below to run just that case
 tests64gc = ["arch64i"]
 
 cachetypes = ["ICache", "DCache"]
-simdir = os.path.expanduser("~/cvw/sim")
+simdir = os.path.expandvars("$WALLY/sim")
 
 if __name__ == '__main__':
     parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
     parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
     parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
+    parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
 
     args = parser.parse_args()
 
-    testcmd = "vsim -do \"do wally-batch.do rv64gc {}\" -c > /dev/null"
+    testcmd = "wsim --sim " + args.sim + " rv64gc {} > /dev/null"
     cachecmd = "CacheSim.py 64 4 56 44 -f {}"
-    
+
     if args.perf:
         cachecmd += " -p"
     if args.dist:
         cachecmd += " -d"
-    
+
     for test in tests64gc:
         print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
+        print(testcmd.format(test))
         os.system(testcmd.format(test))
         for cache in cachetypes:
             print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
-            os.system(cachecmd.format(cache+".log"))
+            os.system(cachecmd.format(args.sim+"/"+cache+".log"))
         print()