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Merge pull request #804 from jordancarlin/dev

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Eliminate more logical operators and replace with bitwise operators
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Rose Thompson 2024-05-16 15:45:18 -05:00 committed by GitHub
commit 9a42aab971
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GPG Key ID: B5690EEEBB952194
3 changed files with 18 additions and 18 deletions
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30
testbench/common/instrNameDecTB.sv
View File

@ -58,17 +58,17 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b010010) name = "BCLRI";
else if (funct7[6:1] == 6'b011010) name = "BINVI";
else if (funct7[6:1] == 6'b001010) name = "BSETI";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP";
else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM";
else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I";
else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1";
else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "ZIP";
else if (funct7 == 7'b0011000 & rs2 == 5'b00000) name = "AES64IM";
else if (funct7 == 7'b0011000 & rs2[4] == 1'b1) name = "AES64KS1I";
else if (funct7 == 7'b0001000 & rs2 == 5'b00010) name = "SHA256SIG0";
else if (funct7 == 7'b0001000 & rs2 == 5'b00011) name = "SHA256SIG1";
else if (funct7 == 7'b0001000 & rs2 == 5'b00000) name = "SHA256SUM0";
else if (funct7 == 7'b0001000 & rs2 == 5'b00001) name = "SHA256SUM1";
else if (funct7 == 7'b0001000 & rs2 == 5'b00110) name = "SHA512SIG0";
else if (funct7 == 7'b0001000 & rs2 == 5'b00111) name = "SHA512SIG1";
else if (funct7 == 7'b0001000 & rs2 == 5'b00100) name = "SHA512SUM0";
else if (funct7 == 7'b0001000 & rs2 == 5'b00101) name = "SHA512SUM1";
else if (funct7 == 7'b0110000) begin
case (rs2)
5'b00000: name = "CLZ";
@ -89,7 +89,7 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b010010) name = "BEXTI";
else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
else if (imm == 12'b011010000111) name = "BREV8";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP";
else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "UNZIP";
else name = "ILLEGAL";
10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I";
else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
@ -181,9 +181,9 @@ module instrNameDecTB(
else if (funct7 == 7'b0010000) name = "SH2ADD";
else if (funct7 == 7'b0000101) name = "MIN";
else if (funct7 == 7'b0100000) name = "ORN";
else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H";
else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK";
else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW";
else if (funct7 == 7'b0000100 & rs2 == 5'b00000) name = "ZEXT.H";
else if (funct7 == 7'b0000100 & op == 7'b0110011) name = "PACK";
else if (funct7 == 7'b0000100 & op == 7'b0111011) name = "PACKW";
else name = "ILLEGAL";
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
else if (funct7 == 7'b0000001) name = "DIVU";

4
testbench/common/loggers.sv
View File

@ -153,7 +153,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
end
end
if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger
if (P.ICACHE_SUPPORTED & I_CACHE_ADDR_LOGGER) begin : ICacheLogger
int file;
string LogFile;
logic resetD, resetEdge;
@ -193,7 +193,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
end
if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger
if (P.DCACHE_SUPPORTED & D_CACHE_ADDR_LOGGER) begin : DCacheLogger
int file;
string LogFile;
logic resetD, resetEdge;

2
testbench/testbench.sv
View File

@ -643,7 +643,7 @@ module testbench;
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
always @(negedge clk) begin
if (INSTR_LIMIT > 0) begin
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
end
end