From 9a17556de45d5ecc7822495736e5c7016a6a7538 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 8 Jun 2021 15:29:22 -0400 Subject: [PATCH] Start to parameterize number of PMP Entries --- wally-pipelined/config/rv32ic/wally-config.vh | 3 +++ wally-pipelined/config/rv64ic/wally-config.vh | 3 +++ wally-pipelined/src/dmem/dmem.sv | 2 +- wally-pipelined/src/ifu/ifu.sv | 4 ++-- wally-pipelined/src/mmu/mmu.sv | 2 +- wally-pipelined/src/mmu/pmpchecker.sv | 6 +++--- wally-pipelined/src/privileged/csr.sv | 2 +- wally-pipelined/src/privileged/csrm.sv | 8 ++++---- wally-pipelined/src/privileged/privileged.sv | 2 +- wally-pipelined/src/wally/wallypipelinedhart.sv | 2 +- 10 files changed, 20 insertions(+), 14 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 078557e1c..096f8df89 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -51,6 +51,9 @@ `define ITLB_ENTRY_BITS 5 `define DTLB_ENTRY_BITS 5 +// Legal number of PMP entries are 0, 16, or 64 +`define PMP_ENTRIES 16 + // Address space `define RESET_VECTOR 32'h80000000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 348d38a33..9dda7f3bf 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -52,6 +52,9 @@ `define ITLB_ENTRY_BITS 5 `define DTLB_ENTRY_BITS 5 +// Legal number of PMP entries are 0, 16, or 64 +`define PMP_ENTRIES 16 + // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 110452043..d05d592cb 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -71,7 +71,7 @@ module dmem ( input logic HWRITE, input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage. input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], // *** this one especially has a large note attached to it in pmpchecker. output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 4a810ad38..4ec40a63b 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -79,8 +79,8 @@ module ifu ( input logic [2:0] HSIZE, HBURST, input logic HWRITE, input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage. - input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. + input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF, output logic ISquashBusAccessF, diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 0cc72f922..3efc4cef6 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -70,7 +70,7 @@ module mmu #(parameter ENTRY_BITS = 3, input logic HWRITE, input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], output logic SquashBusAccess, // *** send to privileged unit output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM, diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 62df15801..f9b15a1cb 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -48,7 +48,7 @@ module pmpchecker ( // boundary. It would be better to store the PMP address registers in a module // somewhere in the CSR hierarchy and do PMP checking _within_ that module, so // we don't have to pass around 16 whole registers. - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], input logic ExecuteAccessF, WriteAccessM, ReadAccessM, @@ -89,9 +89,9 @@ module pmpchecker ( .Match(Regions[0])); assign ActiveRegion[0] = |PMPCFG[0][4:3]; - generate + generate // *** only for PMP_ENTRIES > 0 genvar i; - for (i = 1; i < 16; i++) begin + for (i = 1; i < `PMP_ENTRIES; i++) begin pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[i][4:3]), .CurrentPMPAdr(PMPADDR_ARRAY_REGW[i]), .AdrAtLeastPreviousPMP(AboveRegion[i-1]), diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index fd7f204eb..f1576128f 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -60,7 +60,7 @@ module csr #(parameter output logic STATUS_MXR, STATUS_SUM, output logic STATUS_MPRV, output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, - output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 5cb4a3dc1..89947847f 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -93,7 +93,7 @@ module csrm #(parameter output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, // 64-bit registers in RV64, or two 32-bit registers in RV32 output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, - output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], input logic [11:0] MIP_REGW, MIE_REGW, output logic WriteMSTATUSM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM @@ -171,10 +171,10 @@ module csrm #(parameter endgenerate flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], ALL_ONES, MCOUNTINHIBIT_REGW); - // There are 16 PMPADDR registers, each of which has its own flop + // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop generate genvar i; - for (i = 0; i < 16; i++) begin: pmp_flop + for (i = 0; i < `PMP_ENTRIES-1; i++) begin: pmp_flop flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]); end endgenerate @@ -221,7 +221,7 @@ module csrm #(parameter PMPCFG1: CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG01_REGW[63:31]}; PMPCFG2: CSRMReadValM = PMPCFG23_REGW[`XLEN-1:0]; PMPCFG3: CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG23_REGW[63:31]}; - PMPADDR0: CSRMReadValM = PMPADDR_ARRAY_REGW[0]; + PMPADDR0: CSRMReadValM = PMPADDR_ARRAY_REGW[0]; // *** make configurable PMPADDR1: CSRMReadValM = PMPADDR_ARRAY_REGW[1]; PMPADDR2: CSRMReadValM = PMPADDR_ARRAY_REGW[2]; PMPADDR3: CSRMReadValM = PMPADDR_ARRAY_REGW[3]; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 5dab6b275..503582def 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -68,7 +68,7 @@ module privileged ( output logic [`XLEN-1:0] SATP_REGW, output logic STATUS_MXR, STATUS_SUM, output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, - output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], //*** to be sent up through wallypipelinedhart into the pma/pmp in ifu and dmem. *** is it a bad idea to have this huge bus running all over? + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], output logic [2:0] FRM_REGW ); diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 9473cb587..538f91546 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -120,7 +120,7 @@ module wallypipelinedhart ( logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM; logic DSquashBusAccessM, ISquashBusAccessF; logic [5:0] DHSELRegionsM, IHSELRegionsF; - logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** again, this is a huge bus to be sending all around. + var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1]; logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // signals being sent from privileged unit to pmp/pma in dmem and ifu. assign HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this?